CDC 6000 series

In all the CDC 6000 series computers, the central processor communicates with around seven simultaneously active programs (jobs), which reside in central memory. Instructions from these programs are read into the central processor registers and are executed by the central processor at scheduled intervals. The results are then returned to central memory.

Information is stored in central memory in the form of words. The length of each word is 60 binary digits (bits). The highly efficient address and data control mechanisms involved permit a word to be moved into or out of central memory in as little as 100 nanoseconds.

An extended core storage unit (ECS) provides additional memory storage and enhances the powerful computing capabilities of the CDC 6000 series computers. The unit contains interleaved core banks, each one ECS word (488 bits) wide and an 488 bit buffer for each bank. While nominally slower than CM, ECS included a buffer (cache) that in some applications gave ECS better performance than CM. However, with a more common reference pattern the CM was still faster.

The central processor was the high-speed arithmetic unit that functioned as the workhorse of the computer. It performed the addition, subtraction, and logical operations and all of the multiplication, division, incrementing, indexing, and branching instructions for user programs. Note that in the CDC 6000 architecture, the central processing unit performed no input/output (I/O) operations. Input/Output was totally asynchronous, and performed by peripheral processors.

A 6000 series CPU contained 24 operating registers, designated X0-X7, A0-A7, and B0-B7. The eight X registers were each 60 bits long, and used for most data manipulation—both integer and floating point. The eight B registers were 18 bits long, and generally used for indexing and address storage. Register B0 was hard-wired to always return 0. By software convention, register B1 was generally set to 1. (This often allowed the use of 15-bit instructions instead of 30-bit instructions.) The eight 18-bit A registers were 'coupled' to their corresponding X registers in an interesting way: setting an address into any of registers A1 through A5 caused a memory load of the contents of that address into the corresponding X registers. Likewise, setting an address into registers A6 and A7 caused a memory store into that location in memory from X6 or X7. Registers A0 and X0 were not coupled in this way, so could be used as scratch registers. However A0 and X0 were used when addressing CDCs Extended Core Storage (ECS).

Instructions were either 15 or 30 bits long, so there could be up to four instructions per 60-bit word. A 60-bit word could contain any combination of 15-bit and 30-bit instructions that fit within the word, but a 30-bit instruction could not wrap to the next word. The op codes were six bits long. The remainder of the instruction was either three three-bit register fields (two operands and one result), or two registers with an 18-bit immediate constant. All instructions were 'register to register'. For example, the following COMPASS (assembly language) code loads two values from memory, performs a 60-bit integer add, then stores the result:

SA1   X       SET REGISTER A1 TO ADDRESS OF X; LOADS X1 FROM THAT ADDRESS
SA2   Y       SET REGISTER A2 TO ADDRESS OF Y; LOADS X2 FROM THAT ADDRESS
IX6   X1+X2   LONG INTEGER ADD REGISTERS X1 AND X2, RESULT INTO X6
SA6   Z       SET REGISTER A6 TO ADDRESS OF Z; STORES X6 TO THAT ADDRESS

The central processor used in the CDC 6400 series contained a unified arithmetic element which performed one machine instruction at a time. Depending on instruction type, an instruction could take anywhere from a relatively fast five clock cycles (18-bit integer arithmetic) to as many as 68 clock cycles (60-bit population count). The CDC 6500 was identical to the 6400, but included two identical 6400 CPUs. Thus the CDC 6500 could nearly double the computational throughput of the machine. (But not the I/O throughput; that was still limited by the slowness of external I/O devices served by the same 10 PPs/12 Channels. But many CDC customers worked on compute-bound problems; the 6500 was perfect for them.)

The CDC 6600 computer, like the CDC 6400, has just one central processor. However, its central processor offered much greater efficiency. The processor was divided into 10 individual functional units, each of which was designed for a specific type of operation. All 10 functional units could operate simultaneously, each working on their own operation. The function units provided were: branch, Boolean, shift, long integer add, floating-point add, floating-point divide, two floating-point multipliers, and two increment (18-bit integer add) units. Functional unit latencies were between a very fast three clock cycles (increment add) and 29 clock cycles (floating-point divide).

The 6600 processor could issue a new instruction every clock cycle, assuming that various processor (functional unit, register) resources were available. These resources were kept track of by a scoreboard mechanism. Also contributing to keeping the issue rate high was an instruction stack, which cached the contents of eight instruction words (32 short instructions or 16 long instructions, or a combination). Small loops could reside entirely within the stack, eliminating memory latency from instruction fetches.

Both the 6400 and 6600 CPUs had a cycle time of 100 ns (10 MHz). Due to the serial nature of the 6400 CPU, its exact speed was heavily dependent on instruction mix, but generally around 1 MIPS. Floating-point additions were fairly fast at 11 clock cycles, however floating-point multiplication was very slow at 57 clock cycles. Thus its floating point speed would depend heavily on the mix of operations and could be under 200 kFLOPS. The 6600 was, of course, much faster. With good compiler instruction scheduling, the machine could approach its theoretical peak of 10 MIPS. Floating-point additions took four clock cycles, and floating-point multiplies took 10 clocks (but there were two multiply functional units, so two operations could be processing at the same time.) The 6600 could therefore have a peak floating point speed of 2-3 MFLOPS.

The CDC 6700 computer combined the best features of the other three computers. Like the CDC 6500, it had two central processors. One was a CDC 6400/CDC 6500 central processor with the unified arithmetic section; the other was the more efficient CDC 6600 central processor. The combination made the CDC 6700 the fastest and the most powerful of the CDC 6000 series.

The central processor shares access to central memory with up to ten peripheral processors (PPs). Each peripheral processor is an individual computer with its own 1 μs memory of 4K words, each with 12 bits.[16]^:p.4–2 (They were somewhat similar to CDC 160A minicomputers, sharing the 12-bit word length and portions of the instruction set.)

While the PPs were designed as an interface to the 12 I/O channels, portions of the Chippewa Operating System (COS), and systems derived from it, e.g., SCOPE, MACE, KRONOS, NOS, and NOS/BE, ran on the PPs. Only the PPs have access to the channels and can perform input/output: the transfer of information between central memory and peripheral devices such as disks and magnetic tape units. They relieve the central processor of all input/output tasks, so that it can perform calculations while the peripheral processors are engaged in input/output and operating system functions. This feature promotes rapid overall processing of user programs. Much of the operating system ran on the PPs,[29] thus leaving the full power of the Central Processor available for user programs.

Each peripheral processor can add, subtract, and perform logical operations. Special instructions perform data transfer between processor memory and, via the channels, peripheral devices at up to 1 μs per word. The peripheral processors are collectively implemented as a barrel processor. Each executes routines independently of the others. They are a loose predecessor of bus mastering or direct memory access.

Instructions used a 6-bit op code, thus leaving only 6 bits for an operand. It was also possible to combine the next word's 12 bits, to form an 18-bit address (the size needed to access the full 131,072 words of Central Memory).[16]^:p.4–6

For input or output, each peripheral processor accesses a peripheral device over a communication link called a data channel. One peripheral device can be connected to each data channel; however, a channel can be modified with hardware to service more than one device.

Each peripheral processor can communicate with any peripheral device if another peripheral processor is not using the data channel connected to that device. In other words, only one peripheral processor at a time can use a particular data channel.

Console for CDC 6600

In addition to communication between peripheral devices and peripheral processors, communication takes place between the computer operator and the operating system. This was made possible by the computer console, which had two CRT screens.

This display console was a significant departure from conventional computer consoles of the time, which contained hundreds of blinking lights and switches for every state bit in the machine. (See front panel for an example.) By comparison, the 6000 series console was an elegant design: simple, fast and reliable.

The console screens were calligraphic, not raster based. Analog circuitry steered the electron beams to draw the individual characters on the screen. One of the peripheral processors ran a dedicated program called "DSD" (Dynamic System Display), which drove the console. Coding in DSD needed to be fast as it needed to continually redraw the screen quickly enough to avoid visible flicker.

DSD displayed information about the system and the jobs in process. The console also included a keyboard through which the operator could enter requests to modify stored programs and display information about jobs in or awaiting execution.

A full-screen editor, called O26 (after the IBM model 026 key punch, with the first character made alphabetic due to operating system restrictions), could be run on the operator console. This text editor appeared in 1967—which made it one of the first full-screen editors. (Unfortunately, it took CDC another 15 years to offer FSE, a full-screen editor for normal time-sharing users on CDCs Network Operating System.)

There were also a variety of games that were written using the operator console. These included BAT (a baseball game), KAL (a kaleidoscope), DOG (Snoopy flying his doghouse across the screens), ADC (Andy Capp strutting across the screens), EYE (changed the screens into giant eyeballs, then winked them), PAC (a Pac-Man-like game), a lunar lander simulator, and more.

The minimum hardware requirements of a CDC 6000 series computer system consisted of the computer, including 32,768 words of central memory storage, any combination of disks, disk packs, or drums to provide 24 million characters of mass storage, a punched card reader, punched card punch, printer with controllers, and two 7-track magnetic tape units.

Larger systems could be obtained by including optional equipment such as additional central memory,[30][16] extended core storage (ECS), additional disk or drum units, card readers, punches, printers, and tape units. Graphic plotters and microfilm recorders were also available.

• CDC 405 Card Reader - Unit reads 80-column cards at 1200 cards a minute and 51-column cards at 1600 cards per minute. Each tray holds 4000 cards to reduce the rate of required loading.[31]
• CDC 6602/6612 Console Display
• CDC 6603 Disk System
• CDC 626 Magnetic Tape Transports
• CDC 6671 Communications Multiplexer - supported up to 16 synchronous data connections up to 4800 bps each for Remote Job Entry
• CDC 6676 Communications Multiplexer - supported up to 64 asynchronous data connections up to 300 bps each for timesharing access.
• CDC 6682/6683 Satellite Coupler
• CDC 6681 Data Channel Converter[6]

The CDC 6600 was the flagship mainframe supercomputer of the 6000 series of computer systems manufactured by Control Data Corporation. Generally considered to be the first successful supercomputer, it outperformed its fastest predecessor, the IBM 7030 Stretch, by a factor of three. With performance of up to three megaFLOPS,[32][33] the CDC 6600, of which about 100 were sold,[34] was the world's fastest computer from 1964 to 1969, when it relinquished that status to its successor, the CDC 7600.[35][27]

The CDC 6600 anticipated the RISC design philosophy and, unusually, employed a ones'-complement representation of integers. Its successors would continue the architectural tradition for more than 30 years until the late 1980s, and were the last chips designed with ones'-complement integers.[36]

The CDC 6600 was also the first widespread computer to include a Load–store architecture, with the writing to its address registers triggering memory load or store of data from its data registers.

The first CDC 6600's were delivered in 1965 to the Livermore and Los Alamos National Labs (managed by the University of California). Serial #4 went to the Courant Institute of Mathematical Sciences Courant Institute at NYU in Greenwich Village, New York CIty. The first delivery outside the US went to CERN laboratory near Geneva, Switzerland,[37] where it was used to analyse the two to three million photographs of bubble-chamber tracks that CERN experiments were producing every year. In 1966 another CDC 6600 was delivered to the Lawrence Radiation Laboratory, part of the University of California at Berkeley, where it was used for the analysis of nuclear events photographed inside the Alvarez bubble chamber.[38] The University of Texas at Austin had one delivered for its Computer Science and Mathematics Departments, and installed underground on its main campus, tucked into a hillside with one side exposed, for cooling efficiency.

A CDC 6600 is on display at the Computer History Museum in Mountain View, California.

The CDC 6400, a member of the CDC 6000 series, was a mainframe computer made by Control Data Corporation in the 1960s. The central processing unit was architecturally compatible with the CDC 6600. In contrast to the 6600, which had 10 parallel functional units which could work on multiple instructions at the same time, the 6400 had a unified arithmetic unit, which could only work on a single instruction at a time. This resulted in a slower, lower-performance CPU, but one that cost significantly less. Memory, peripheral processor-based input/output (I/O), and peripherals were otherwise identical to the 6600.

In 1966, the Computing Center (German: Rechenzentrum) of the RWTH Aachen University acquired a CDC 6400, the first Control Data supercomputer in Germany and the second one in Europe after the European Organization for Nuclear Research (CERN). It served the entire university also by 64 remote-line teletypes (TTY) until it was replaced by a CDC Cyber 175 computer in 1976.[39]

• 
  Operator console of the CDC 6400 with four magnetic tape memory units in the background with a magnetic tape controller unit in front of them at the Rechenzentrum (Computer Center) of RWTH Aachen University, Germany (1970).
• 
  Seven-track magnetic tape memory units (CDC 604) at the Rechenzentrum (Computer Center) of RWTH Aachen University, Germany (1970)
• 
  CDC 6400 used by the US Navy

CDC 6500

Open panels of the CDC 6500 undergoing restoration at Living Computers: Museum + Labs in Seattle.
Developer	Seymour Cray
Manufacturer	Control Data Corporation
Product family	CDC 6000 series
Type	Supercomputer
Release date	1967 (1967)
Introductory price	$8 million ~ equivalent to $65,948,498 in 2019
Operating system	SCOPE, NOS
CPU	Dual 6400, up to 40 MHz
Memory	65,000 60-bit words
Display	DD60
Mass	from 10,000 pounds (5.0 short tons; 4.5 t).
Predecessor	IBM 7030 Stretch
Successor	CDC 7600

The CDC 6500, which features a dual CPU 6400,[40] is the third supercomputer in the 6000 series manufactured by the Control Data Corporation and designed by supercomputer pioneer Seymour Cray.[23] The first 6500 was announced in 1964 and was delivered in 1967.[41]

It includes twelve different independent computers. Ten are peripheral and control processors, each of which have a separate memory and can run programs separately from each other and the two 6400 central processors.[6] Instead of being air-cooled, it has a liquid refrigeration system and each of the three bays of the computer has its own cooling unit.[42]

CDC 6500 systems were installed at:

• Michigan State University - bought in 1968, meant to replace its CDC 3600, and it was the only academic mainframe on campus.[43]
• CERN - upgraded from a 6400 to a 6500 in April 1969.[44]
• the technical lab at the Patrick Air Force Base in 1978.[45]
• the Laboratory of Computing Techniques and Automation in the Joint Institute for Nuclear Research (USSR) - originally bought CDC 6200 in 1972, later upgraded to 6500, retired in 1995

• 
  CDC 6500 (right) and other equipment
• 
  Detailed image of the CDC 6500 at LCM+L
• 
  Detailed image of the CDC 6500 at LCM+L

Composed of a 6600 and a 6400, the CDC 6700 was the most powerful of the 6000 series.