NEAT chipset

The NEAT chipset descended from the first chipset that C&T had developed for IBM XT-compatible systems, which was based around the 82C100[2] "XT controller" chip. 82C100 incorporated the functionality of what had been, until its invention, discrete TTL chips on the XT's mainboard, namely:[3]

• 8284 clock generator
• 8288 bus controller
• 8254 Programmable Interval Timer
• 8255 parallel I/O interface
• 8259 Programmable Interrupt Controller
• 8237 DMA controller
• 8255 Programmable Peripheral Interface (PPI)
• DRAM/SRAM controller
• XT Keyboard controller

IBM PC compatibility is provided by C&T's 82C206 Integrated Peripheral Controller (IPC), introduced by C&T in 1986. This chip, like its predecessor the 82C100, provided equivalent functionality to the TTL chips on the PC/AT's mainboard, namely:[1]

• 82284 clock generator
• 82288 bus controller
• 8254 Programmable Interval Timer
• two 8259 Programmable Interrupt Controllers
• two 8237 DMA controllers
• 74LS612 Memory Mapper chip
• MC146818 NVRAM/RTC chip

NEAT CS8221's predecessor, called CS8220, required five chips[4] (buffers and memory controllers) for a virtually complete motherboard, while NEAT required only four and added support for separate ISA bus clocks.[5] The eventual successor to the NEAT chipset, 82C235 Single Chip AT (SCAT), amalgamated all of the chips of the NEAT chipset into a single chip.[6]

Other manufacturers produced equivalent chips. OPTi, for example, produced a two-chip "AT controller" chipset comprising the OPTi 82C206 and 82C495XLC, which was found in many early 80486 and Pentium AT-compatible machines. The OPTi 82C206 is pin and function compatible with C&T's 82C206. The 82C495XLC incorporated the additional memory controller and shadow RAM support.[3]