National Semiconductor SC/MP

Like most 8-bit microprocessors of the era, the SC/MP is based around a 16-bit address and an 8-bit data bus. To lower pin count, the external address bus contains only 12 pins, sharing 4 pins from the data bus to create a complete 16-bit address. Internally, the program counter is twelve bits wide, and there are separate instructions to set the upper four bits. This provides a memory map of sixteen four-kilobyte pages, and program code could not refer to code or data outside its own page. Internally it provided five registers plus the program counter, but no stack pointer or subroutine capability.

A unique feature of the SM/MP was a shared daisy-chained control line that allowed multiple SC/MP, or more commonly a single SC/MP and related direct memory access controllers, to share access to a single main memory. When any one of the chips on the bus desired access to memory, it would set the ENOUT pin high, thereby signalling the other chip's ENIN pins that they had to release the bus. With other processors, this would normally require external logic implemented by the board designers to pause the CPU to the same end, often with some complexity due to the internal instruction timing that was not visible to the external circuits. In the SC/MP this was all included internally so a single line on the circuit board was all that was needed to implement this feature.

The original idea was to ease the creation of microcontroller-like applications containing an SC/MP, one or more DMA controllers, and a single shared memory. Designed specifically to be as low-cost as possible in terms of an overall system, the desire to lower the cost of the SC/MP itself also led to decisions about the bit-serial ALU and the inclusion of serial input/output lines to eliminate the need for a separate UART (this feature was removed in the later SC/MP III).