Numerically-controlled oscillator

An NCO generally consists of two parts:

• A phase accumulator (PA), which adds to the value held at its output a frequency control value at each clock sample.
• A phase-to-amplitude converter (PAC), which uses the phase accumulator output word (phase word) usually as an index into a waveform look-up table (LUT) to provide a corresponding amplitude sample. Sometimes interpolation is used with the look-up table to provide better accuracy and reduce phase error noise. Other methods of converting phase to amplitude, including mathematical algorithms such as power series can be used, particularly in a software NCO.

Figure 1: Numerically-controlled oscillator with optional quadrature output

When clocked, the phase accumulator (PA) creates a modulo-2^N sawtooth waveform which is then converted by the phase-to-amplitude converter (PAC) to a sampled sinusoid, where N is the number of bits carried in the phase accumulator. N sets the NCO frequency resolution and is normally much larger than the number of bits defining the memory space of the PAC look-up table. If the PAC capacity is 2^M, the PA output word must be truncated to M bits as shown in Figure 1. However, the truncated bits can be used for interpolation. The truncation of the phase output word does not affect the frequency accuracy but produces a time-varying periodic phase error which is a primary source of spurious products. Another spurious product generation mechanism is finite word length effects of the PAC output (amplitude) word.[4]

The frequency accuracy relative to the clock frequency is limited only by the precision of the arithmetic used to compute the phase.[4] NCOs are phase- and frequency-agile, and can be trivially modified to produce a phase-modulated or frequency-modulated output by summation at the appropriate node, or provide quadrature outputs as shown in the figure.

A binary phase accumulator consists of an N-bit binary adder and a register configured as shown in Figure 1.[5] Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size ${\displaystyle \Delta F}$, the integer value of the FCW.[6] In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle latency but allows the adder to operate at a higher clock rate.[2]

Figure 2: Normalized phase accumulator output

The adder is designed to overflow when the sum of the absolute value of its operands exceeds its capacity (2^N−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder ${\displaystyle \phi _{n}}$, called the residual, is stored in the register and the cycle repeats, starting this time from ${\displaystyle \phi _{n}}$ (see figure 2).[5] Since a phase accumulator is a finite state machine, eventually the residual at some sample K must return to the initial value ${\displaystyle \phi _{0}}$. The interval K is referred to as the grand repetition rate (GRR) given by

${\displaystyle {\mbox{GRR}}={\frac {2^{N}}{{\mbox{GCD}}(\Delta F,2^{N})}}}$

where GCD is the greatest common divisor function. The GRR represents the true periodicity for a given ${\displaystyle \Delta F}$ which for a high resolution NCO can be very long.[5] Usually we are more interested in the operating frequency determined by the average overflow rate, given by[6]

${\displaystyle F_{out}={\frac {\Delta F}{2^{N}}}F_{clock}}$      (1)

The frequency resolution, defined as the smallest possible incremental change in frequency, is given by[6]

${\displaystyle F_{res}={\frac {F_{clock}}{2^{N}}}}$      (2)

Equation (1) shows that the phase accumulator can be thought of as a programmable non-integer frequency divider of divide ratio ${\displaystyle \Delta F/2^{N}}$.[4]

The phase-amplitude converter creates the sample-domain waveform from the truncated phase output word received from the PA. The PAC can be a simple read only memory containing 2^M contiguous samples of the desired output waveform which typically is a sinusoid. Often though, various tricks are employed to reduce the amount of memory required. This include various trigonometric expansions,[7] trigonometric approximations[5] and methods which take advantage of the quadrature symmetry exhibited by sinusoids.[8] Alternatively, the PAC may consist of random access memory which can be filled as desired to create an arbitrary waveform generator.

Spurious products are the result of harmonic or non-harmonic distortion in the creation of the output waveform due to non-linear numerical effects in the signal processing chain. Only numerical errors are covered here. For other distortion mechanisms created in the digital-to-analog converter see the corresponding section in the direct-digital synthesizer article.

• Digital-to-analog converter (DAC)
• Digitally controlled oscillator (DCO)
• Direct digital synthesis (DDS)