Op amp integrator

Integrator circuit

The circuit operates by passing a current that charges or discharges the capacitor C_F during the time under consideration, which strives to retain the virtual ground condition at the input by off-setting the effect of the input current. Referring to the above diagram, if the op-amp is assumed to be ideal, nodes v₁ and v₂ are held equal (missing label v₁ at the + input), and so v₂ is a virtual ground. The input voltage passes a current ${\displaystyle {\frac {v_{in}}{R_{1}}}}$ through the resistor producing a compensating current flow through the series capacitor to maintain the virtual ground. This charges or discharges the capacitor over time. Because the resistor and capacitor are connected to a virtual ground, the input current does not vary with capacitor charge and a linear integration of output is achieved.

The circuit can be analyzed by applying Kirchhoff's current law at the node v₂, keeping ideal op-amp behaviour in mind.

${\displaystyle i_{\text{1}}=I_{\text{B}}+i_{\text{F}}}$

${\displaystyle I_{\text{B}}=0}$ in an ideal op-amp, so:

${\displaystyle i_{\text{1}}=i_{\text{F}}}$

Furthermore, the capacitor has a voltage-current relationship governed by the equation:

${\displaystyle I_{\text{C}}=C{\frac {dV_{\text{c}}}{dt}}}$

Substituting the appropriate variables:

${\displaystyle {\frac {v_{\text{in}}-v_{\text{2}}}{R_{\text{1}}}}=C_{\text{F}}{\frac {d(v_{\text{2}}-v_{\text{o}})}{dt}}}$

${\displaystyle v_{2}=v_{1}=0}$ in an ideal op-amp, resulting in:

${\displaystyle {\frac {v_{\text{in}}}{R_{\text{1}}}}=-C_{\text{F}}{\frac {dv_{\text{o}}}{dt}}}$

Integrating both sides with respect to time:

${\displaystyle \int _{0}^{t}{\frac {v_{\text{in}}}{R_{\text{1}}}}\ dt\ =-\int _{0}^{t}C_{\text{F}}{\frac {dv_{\text{o}}}{dt}}\,dt}$

If the initial value of v_o is assumed to be 0 V, this results in a DC error of:[2]

${\displaystyle v_{\text{o}}=-{\frac {1}{R_{\text{1}}C_{\text{F}}}}\int _{0}^{t}v_{\text{in}}\,dt}$

Practical integrator

The ideal circuit is not a practical integrator design for a number of reasons. Practical op-amps have a finite open-loop gain, an input offset voltage and input bias currents (${\displaystyle I_{B}}$). This can cause several issues for the ideal design; most importantly, if ${\displaystyle v_{\text{in}}=0}$, both the output offset voltage and the input bias current ${\displaystyle I_{B}}$ can cause current to pass through the capacitor, causing the output voltage to drift over time until the op-amp saturates. Similarly, if ${\displaystyle v_{\text{in}}}$ were a signal centered about zero volts (i.e. without a DC component), no drift would be expected in an ideal circuit, but may occur in a real circuit. To negate the effect of the input bias current, it is necessary to set:

${\displaystyle R_{\text{om}}=R_{1}||R_{F}||R_{L}}$. The error voltage then becomes:

${\displaystyle V_{\text{E}}=\left({\frac {R_{\text{F}}}{R_{1}}}+1\right)V_{IOS}}$

The input bias current thus causes the same voltage drops at both the positive and negative terminals.

Also, in a DC steady state, the capacitor acts as an open circuit. The DC gain of the ideal circuit is therefore infinite (or in practice, the open-loop gain of a non-ideal op-amp). To counter this, a large resistor ${\displaystyle R_{F}}$ is inserted in parallel with the feedback capacitor, as shown in the figure above. This limits the DC gain of the circuit to a finite value, and hence changes the output drift into a finite, preferably small, DC error. Referring to the above diagram:

${\displaystyle V_{\text{E}}=\left({\frac {R_{\text{F}}}{R_{1}}}+1\right)\left(V_{IOS}+I_{BI}\left(R_{\text{F}}\parallel R_{1}\right)\right)}$

where ${\displaystyle V_{IOS}}$ is the input offset voltage and ${\displaystyle I_{BI}}$ is the input bias current on the inverting terminal. ${\displaystyle R_{F}\parallel R_{1}}$ indicates two resistance values in parallel.