Sarita Adve

In the areas of memory consistency models for multiprocessors, Adve co-developed the memory models for the C++ and Java programming languages, which are based on her early work on data-race-free models. In hardware reliability she co-developed the concept of lifetime reliability aware architectures and dynamic reliability management. In power management she led the design of one of the first systems to implement cross-layer energy management. She co-authored some of the first papers on exploiting Instruction level parallelism for memory system performance. She also led the development of the widely used RSIM architecture simulator, which can be used to evaluate shared-memory multiprocessors with Instruction level parallelism.

Adve completed a Bachelor of Technology degree in electrical engineering at Indian Institute of Technology Bombay in 1987. She subsequently completed a Master of Science (1989) and Ph.D. (1993) in computer science at the University of Wisconsin–Madison.[2][3] Before joining Illinois, Adve was a member of faculty at Rice University from 1993 to 1999. She served on the NSF CISE directorate's advisory committee from 2003 to 2005 and on the expert group to revise the Java memory model from 2001 to 2005. She served as chair of ACM SIGARCH from 2015–2019.[4]

Adve received the Ken Kennedy Award in 2018,[5] the ACM SIGARCH Maurice Wilkes award in 2008,[6] an IBM faculty award in 2005, was named a UIUC University Scholar in 2004,[7] received an Alfred P. Sloan Research Fellowship in 1998, an IBM University Partnership award in 1997 and 1998, and a National Science Foundation CAREER award in 1995. She was named a Fellow of the ACM in 2010.[8] She was the winner of the 2012 ABIE Award for Innovation from the Anita Borg Institute.[9][10] In 2020, she was elected to the American Academy of Arts and Sciences.[11]

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