IBM z15 (microprocessor)
The z15 is a microprocessor made by IBM for their IBM Z mainframe computers, announced on September 12, 2019.[2]
| General information | |
|---|---|
| Launched | 2019 |
| Designed by | IBM |
| Performance | |
| Max. CPU clock rate | 5.2[1] GHz |
| Cache | |
| L1 cache | 128 KB I-L1 128 KB D-L1 per core |
| L2 cache | 4 MB I-L2 4 MB D-L2 per core |
| L3 cache | 256 MB shared |
| Architecture and classification | |
| Min. feature size | 14 nm[1] |
| Instruction set | z/Architecture |
| Physical specifications | |
| Cores |
|
| History | |
| Predecessor | z14 |
Description
The Processor Unit chip (PU chip) has 12 cores. The z15 cores support two-way simultaneous multithreading.[3]
The cores implement the CISC z/Architecture with a superscalar, out-of-order pipeline. New in z15 is an on-chip Nest Accelerator Unit, shared by all cores, to accelerate compression.[3]
The cache (e.g. level 3) is doubled from the previous generation z14, while the "L4 Cache increased from 672MB to 960MB, or +43%" with the new add-on chip System Controller (SC) SCM. Both it and all levels of cache in the main processor from level 1 use eDRAM, instead of the traditionally used SRAM. "A five-CPC drawer system has 4800 MB (5 x 960 MB) of shared L4 cache."
See also
References
- "IBM z15 (z15)". IBM.
- "IBM Unveils z15 With Industry-First Data Privacy Capabilities" (Press release). IBM. September 12, 2019.
- IBM z15 (8561) Technical Guide (PDF). September 2019. SG24-8851-00. Retrieved September 14, 2019.