Ling adder

In electronics, an adder is a combinatorial or sequential logic element which computes the n-bit sum of two numbers. The family of Ling adders is a particularly fast adder and is designed using H. Ling's equations and generally implemented in BiCMOS. Samuel Naffziger of Hewlett Packard presented an innovative 64 bit adder in 0.5 μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4. See Naffzinger's paper below for more details.

  1. H. Ling, "High Speed Binary Parallel Adder", IEEE Transactions on Electronic Computers, EC-15, p. 799-809, October, 1966.
  2. H. Ling, "High-Speed Binary Adder", IBM J. Res. Dev., vol.25, p. 156-66, 1981.
  3. R. W. Doran, "Variants on an Improved Carry Look-Ahead Adder", IEEE Transactions on Computers, Vol.37, No.9, September 1988.
  4. N. T. Quach, M. J. Flynn, "High-Speed Addition in CMOS", IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
  5. S. Naffziger, "A Sub-Nanosecond 0.5um 64b Adder Design", Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p. 362 –363.
  6. S. Naffziger, "High Speed Addition Using Ling's Equations and Dynamic CMOS Logic", U.S. Patent No. 5,719,803, Issued: February 17, 1998.


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