List of VIA microprocessor cores

This page lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common.

This list is incomplete; you can help by adding missing items with reliable sources.

Cyrix design (Cyrix III)
Marketing
name		CoreFrequencyFront-side busL1-cacheL2-cacheFPU
speed		Pipeline
stages		Typical powerVoltageProcess
Cyrix IIIJoshua350-450 MHz100-133 MHz64 KB256 KB100%?13-16 W2.2 V180 nm Al

Centaur Technology design

Cyrix III, C3
Marketing
name		CoreFrequencyFront-side busL1 cacheL2 cacheFPU
speed		Pipeline
stages		Typical powerVoltageProcess
Cyrix III, C3, 1GigaProSamuel (C5A)466-733 MHz100-133 MHz128 KB0 KB50%126.8-10.6 W1.8-2.0 V180 nm Al
Cyrix III, C3, 1GigaPro, Eden ESP, XP 2000+Samuel 2 (C5B)600-800 MHz100-133 MHz128 KB64 KB50%125.8-6.6 W1.5-1.65 V150 nm Al
C3, Eden ESPEzra (C5C)733-933 MHz100-133 MHz128 KB64 KB50%125.3-5.9 W1.35 V130 nm Al
C3Ezra-T (C5N)800-1000 MHz100-133 MHz64 KB64 KB50%125.3-11.8 W1.35 V130 nm Al

C3, C7
Marketing
name		CoreFrequencyFront-side busL1 cacheL2 cacheFPU
speed		Pipeline
stages		Typical powerVoltageProcess
C3, Eden ESP, Eden-NNehemiah (C5XL)800-1400 MHz133 MHz64 KB64 KB100%1615-19 W1.25-1.45 V130 nm Cu
C3Nehemiah+ (C5P)1-1.4 GHz133 MHz32 KB64 KB100%1611-12 W1.25 V130 nm Cu
C7, C7-D, C7-M, Eden, Eden ULVEsther (C5J)0.4-2.0 GHz400-533 MT/s32 KB128 KB100%1612-20 W0.9-1.1(?) V90 nm SOI
Series Model Core Frequency
[MHz]		 Front-side bus
[MHz]		 Year Process
[nm]		 Package size
[mm2]		 Power
[W]		 L2 cache
[K]		 L1 I/D cache
[K]		 Performance
[SPEC2000]
Eden Eden ESPSamuel 2 300–60066/100/133200115035×352.5–66464/64Un­known
Eden ESPNehemiah 667–1000133/2002003–200413035×356–76464/64Un­known
Eden-NNehemiah 533–1000133200313015×152.5–76464/64Un­known
EdenEsther 400–1500400–8002006–20079030<7.512832/32Un­known
Eden X2Un­known 800Un­known20114011×6Un­knownUn­knownUn­knownUn­known
C3 C3Samuel 2 667–800100–1332001150Un­known136464/64Un­known
C3Ezra 800–1000100–1332002130Un­known8.3–106464/64Un­known
C3Nehemiah 1000–1400133–200200313035×3515–216464/64Un­known
C3-MNehemiah 1000–1400133–200200313035×3511–196464/64Un­known
C7 C7-DEsther 1500–180040020069021×2120–2512816/16Un­known
C7-MEsther 1000–200040020059021×2112–2012816/16Un­known
C7Esther 1500–200080020079021×2112–2012816/16Un­known

Nano
Series Model Core Frequency
[MHz]		 Front-side bus
[MHz]		 Year Process
[nm]		 Package size
[mm2]		 Power
[W]		 L2 cache
[K]		 L1 I/D cache
[K]		 Performance
[SPEC2000]
QuadCore QuadCoreIsaiah 1000-1460106620114021×2127.54× 1024[5]4× 64/6430.1/24.1 rate[6]

CHA[7][8][9]
  • Currently in development. Details listed below are subject to change,
  • 8 cores + "NCORE" neural processor for AI acceleration.
  • supports: MMX SSE SSE2 SSE3 SSSE3 SSE4.1 SSE4.2 AES AVX AVX2 FMA3 SHA AVX512 AVX512F AVX512CD AVX512BW AVX512DQ AVX512VL AVX512IFMA AVX512VBMI.
Marketing
name		 Code nameCoreNumber of coresFrequencyMicroarchitecture L1 cache L2 cache L3 cacheAnnounced Expected ReleaseProcess Socket Type Pipeline stages PCIe Lanes
unknown CHACNS82.5 GHzCNS[10] 32 KiB 256 KiB16 MB2019 2H 2020[11] 16 nm LGA 20-22 44[12]

See also

References
  1. "IA-32 implementation: VIA Cyrix III". sandpile.org. Archived from the original on 2007-07-09. Retrieved 2007-07-23.
  2. "IA-32 implementation: VIA C3". sandpile.org. Archived from the original on 2007-07-17. Retrieved 2007-07-23.
  3. "IA-32 implementation: VIA C7". sandpile.org. Archived from the original on 2007-06-30. Retrieved 2007-07-23.
  4. "VIA Nano X2 SPEC2000 ratio and rate scores". Via.com. Archived from the original on 7 February 2014. Retrieved 3 February 2014.
  5. "VIA QuadCore Processor". Via.com. Retrieved 2014-02-03.
  6. "VIA Nano X2 Whitepaper" (PDF). Via.com. Archived from the original (PDF) on 27 May 2012. Retrieved 3 February 2014.
  7. Nov 18th, btarunr; Discuss, 2019 22:10. "VIA CenTaur Develops a Multi-core x86 Processor for Enterprise with in-built AI Hardware". TechPowerUp. Retrieved 2020-07-28.CS1 maint: numeric names: authors list (link)
  8. Feb 18th, btarunr; Discuss, 2020 06:36. "VIA CenTaur CHA NCORE AI CPU Pictured, a Socketed LGA Package". TechPowerUp. Retrieved 2020-07-28.CS1 maint: numeric names: authors list (link)
  9. "CHA - Microarchitectures - Centaur Technology - WikiChip". en.wikichip.org. Retrieved 2020-07-28.
  10. "VIA x86 AI processor architecture, performance announcement: comparable to Intel 32 core". Small Tech News. December 11, 2019.
  11. Dec 9th, btarunr; Discuss, 2019 18:25. "Centaur Releases In-Depth Analysis from The Linley Group for its NCORE-Equipped x86 Processor". TechPowerUp. Retrieved 2020-08-30.CS1 maint: numeric names: authors list (link)
  12. "World's First High-Performancex86 SoCwithIntegrated AI Coprocessor" (PDF). centtech. p. 4.
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