M-PHY

M-PHY is a high speed data communications physical layer protocol standard developed by the MIPI Alliance, PHY Working group, and targeted at the needs of mobile multimedia devices.[1] The specification's details are proprietary to MIPI member organizations, but a substantial body of knowledge can be assembled from open sources. A number of industry standard settings bodies have incorporated M-PHY into their specifications including Mobile PCI Express,[2][3][4][5][6][7][8] Universal Flash Storage,[9][10][11] and as the physical layer for SuperSpeed Inter-Chip USB.[12][13][14][15][16][17]

M-PHY
MIPI M-PHY
Year created2011
Created byMIPI Alliance
SupersedesD-PHY
Width in bits1-4 lanes, w/adaptive discovery (depending on higher-level protocol)
Speedup to 11.6 Gbit/s per data lane
Styleserial, embedded clock
External interfaceyes, with optical media converter
Websitehttps://mipi.org/specifications/m-phy

To support high speed, M-PHY is generally transmitted using differential signaling over impedance controlled traces between components. When use on a single circuit card, the use of electrical termination may be optional. Options to extend its range could include operation over a short flexible flat cable, and M-PHY was designed to support optical media converters allowing extended distance between transmitters and receivers, and reducing concerns with electromagnetic interference.[15]

Applications

M-PHY (like its predecessor D-PHY) is intended to be used in high-speed point-to-point communications, for example video Camera Serial Interfaces. The CSI-2 interface was based on D-PHY (or C-PHY), while the newer CSI-3 interface is based on M-PHY. M-PHY was designed to supplant D-PHY in many applications, but this is expected to take a number of years.

The M-PHY the physical layer is also used in a number of different high-speed emergent industry standards, DigRF (High speed radio interface), MIPI LLI (Low latency memory interconnect for multi-processors systems), and one possible physical layer for the UniPro protocol stack.

Signaling speed and gears

M-PHY supports a scalable variety of signaling speeds, ranging from 10 kbit/s to over 11.6 Gbit/s per lane. This is accomplished using two different major signaling/speed modes, a simple low-speed (using PWM) mode and high speed (using 8b10b).[18] Communications goes on in bursts, and the design of both high-speed and low-speed forms allows for extended periods of idle communications at low-power, making the design particularly suitable for mobile devices.

Within each signaling method, a number of standard speeds, known as "gears", is defined, with the expectation that additional gears will be defined in future versions of the standard.[19]

References


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