PDP-11 architecture

Sixteen-bit words are stored little-endian (with least significant bytes first). Thirty-two-bit data—supported as extensions to the basic architecture, e.g., floating point in the FPU Instruction Set, double-words in the Extended Instruction Set or long data in the Commercial Instruction Set—are stored in more than one format, including an unusual middle-endian format[2][3] sometimes referred to as "PDP-endian".

The PDP-11's 16-bit addresses can address 64 KB. By the time the PDP-11 yielded to the VAX, 8-bit bytes and hexadecimal notation were becoming standard in the industry; however, numeric values on the PDP-11 always use octal notation, and the amount of memory attached to a PDP-11 is always stated as a number of words. The basic logical address space is 32K words, but the high 4K of physical address space (addresses 160000₈ through 177777₈ in the absence of memory management) are not populated because input/output registers on the bus respond to addresses in that range. So originally, a fully loaded PDP-11 had 28K words.

The processor reserves low memory addresses for two-word vectors that give a program counter and processor status word with which to begin a service routine. When an I/O device interrupts a program, it places the address of its vector on the bus to indicate which service routine should take control. The lowest vectors are service routines to handle various types of trap. Traps occur on some program errors, such as an attempt to execute an undefined instruction; and also when the program executes an instruction such as BPT, EMT, IOT, or TRAP to request service from the operating system.

The article PDP-11 describes how the 16-bit logical address space became an insurmountable limitation. During the life of the PDP-11, the following techniques were used to work around the limitation:

• Later-model PDP-11 processors included memory management to support virtual addressing. The physical address space was extended to 18 or 22 bits, hence allowing up to 256 KB or 4 MB of RAM. The logical address space (that is, the address space available at any moment without changing the memory mapping table) remained limited to 16 bits.
• Some models, beginning with the PDP-11/45, can be set to use 32K words (64 KB) as the "instruction space" for program code and a separate 32K words of "data space". Some operating systems—notably Unix since edition V7, and RSX11-M+—rely on this feature.
• Programming techniques, such as overlaying a block of stored instructions or data with another as needed, can conceal paging issues from the application programmer. For example, the Modula-2 compiler produces code under which the run-time system swaps 8 Kb pages into memory as individual procedures receive control. (See the external reference here.)

The following eight modes can be applied to any general register. Their effects when applied to R6 (the stack pointer, SP) and R7 (the program counter, PC) are set out separately in the following sections.

In index and index deferred modes, X is a 16-bit value taken from a second word of the instruction. In double-operand instructions, both operands can use these modes. Such instructions are three words long.

Autoincrement and autodecrement operations on a register are by 1 in byte instructions, by 2 in word instructions, and by 2 whenever a deferred mode is used, since the quantity the register addresses is a (word) pointer.

When R7 (the program counter) is specified, four of the addressing modes naturally yield useful effects:

The only common use of absolute mode, whose syntax combines immediate and deferred mode, is to specify input/output registers, as the registers for each device have specific memory addresses. Relative mode has a simpler syntax and is more typical for referring to program variables and jump destinations. A program that uses relative mode (and relative deferred mode) exclusively for internal references is position-independent; it contains no assumptions about its own location, so it can be loaded into an arbitrary memory location, or even moved, with no need for its addresses to be adjusted to reflect its location (relocated). In computing such addresses relative to the current location, the processor performed relocation on the fly.

Immediate and absolute modes are merely autoincrement and autoincrement deferred mode, respectively, applied to PC. When the auxiliary word is "in the instruction" as the above table says, the PC for the next instruction is automatically incremented past the auxiliary word. As PC always points to words, the autoincrement operation is always by 2.

R6, also written SP, is used as a hardware stack for traps and interrupts. A convention enforced by the set of modes the PDP-11 provides is that a stack grows downward—toward lower addresses—as items are pushed onto it. When a mode is applied to SP, or to any register the programmer elects to use as a software stack, the addressing modes have the following effects:

Although software stacks can contain bytes, SP is always a stack of words. Autoincrement and autodecrement operations on SP is always by 2.

The high-order four bits specify the operation to be performed (with bit 15 generally selecting word versus byte addressing). Two groups of six bits specify the source operand addressing mode and the destination operand addressing mode, as defined above.

The ADD and SUB instructions use word addressing, and have no byte-oriented variations.

Some two-operand instructions utilize an addressing mode operand and an additional register operand:

Where a register pair is used (written below as "(Reg, Reg+1)", the first register contains the low-order portion of the operand and must be an even numbered register. The next higher numbered register contains the high-order portion of the operand (or the remainder). An exception is the multiply instruction; Reg may be odd, but if it is, the high 16 bits of the result are not stored.

The high-order ten bits specify the operation to be performed, with bit 15 generally selecting byte versus word addressing. A single group of six bits specifies the operand as defined above.

In most branch instructions, whether the branch is taken is based on the state of the condition codes. A branch instruction is typically preceded by a two-operand CMP (compare) or BIT (bit test) or a one-operand TST (test) instruction. Arithmetic and logic instructions also set the condition codes. In contrast to Intel processors in the x86 architecture, MOV instructions set them too, so a branch instruction could be used to branch depending on whether the value moved was zero or negative.

The high-order byte of the instruction specifies the operation. Bits 9 through 15 are the op-code, and bit 8 is the value of the condition code calculation which results in the branch being taken. The low-order byte is a signed word offset relative to the current location of the program counter. This allows for forward and reverse branches in code.

The limited range of the branch instructions meant that, as code grew, the target addresses of some branches would become unreachable. The programmer would change the one-word BR to the two-word JMP instruction from the next group. As JMP has no conditional forms, the programmer would change BEQ to a BNE that branched around a JMP.

SOB (Subtract One and Branch) is another conditional branch instruction. The specified register is decremented by 1, and if the result is not zero, a reverse branch is taken based on the 6 bit word offset.

The JSR instruction could save any register on the stack. Programs that did not need this feature specified PC as the register (JSR PC,address) and the routine returned using RTS PC. If a routine were called with, for instance, "JSR R4, address", then the old value of R4 would be on the top of the stack and the return address (just after JSR) would be in R4. This let the routine gain access to values coded in-line by specifying (R4)+, or to in-line pointers by specifying @(R4)+. The autoincrementation moved past these data, to the point at which the caller's code resumed. Such a routine would have to specify RTS R4 to return to its caller.

The four condition codes in the processor status word (PSW) are

• N indicating a negative value
• Z indicating a zero (equal) condition
• V indicating an overflow condition, and
• C indicating a carry condition.

Instructions in this group were what Digital called "micro-programmed": A single bit in the instruction word referenced a single condition code. The assembler did not define syntax to specify every combination, but the symbols SCC and CCC assembled an instruction that set or cleared, respectively, all four condition codes.

Clearing or setting none of the condition codes (opcodes 000240 and 000260, respectively) could effectively be considered as no-operation instructions. In fact, the NOP mnemonic assembled into 000240.

Extended Instruction Set (EIS)

The EIS was an option for 11/35/40 and 11/03, and was standard on newer processors.

• MUL, DIV multiply and divide integer operand to register pair
• ASH, ASHC arithmetic - shift a register or a register pair. For a positive number it will shift left, and right for a negative one.

Floating Instruction Set (FIS)

The FIS instruction set was an option for the PDP-11/35/40 and 11/03

• FADD, FSUB, FMUL, FDIV only for single-precision operating on stack addressed by register operand

Floating Point Processor (FPP)

This was the optional floating point processor option for 11/45 and most subsequent models.

• full floating point operations on single- or double-precision operands, selected by single/double bit in Floating Point Status Register
• single-precision floating point data format predecessor of IEEE 754 format: sign bit, 8-bit exponent, 23-bit mantissa with hidden bit 24

Commercial Instruction Set (CIS)

The CIS was implemented by optional microcode in the 11/23/24, and by an add-in module in the 11/44 and in one version of the 11/74. It provided string and decimal instructions used by COBOL and Dibol.

Access to Processor Status Word (PSW)

The PSW was mapped to memory address 177 776, but instructions found on all but the earliest PDP-11s gave programs more direct access to the register.

• SPL (set priority level)
• MTPS (move to Processor Status)
• MFPS (move from Processor Status)

Access to other memory spaces

On PDP-11s that provided multiple instruction spaces and data spaces, a set of non-orthogonal Move instructions gave access to other spaces. For example, routines in the operating system that handled run-time service calls would use these instructions to exchange information with the caller.

• MTPD (move to previous data space)
• MTPI (move to previous instruction space)
• MFPD (move from previous data space)
• MFPI (move from previous instruction space)

Over the life of the PDP-11, subtle differences arose in the implementation of instructions and combinations of addressing modes, though no implementation was regarded as correct. The inconsistencies did not affect ordinary use of the PDP-11.

PDP-11 processor speed varied by model, memory configuration, op code, and addressing modes. Instruction timing had up to three components, execute/fetch of the instruction itself and access time for the source and the destination. The last two components depended on the addressing mode. For example, on the PDP-11/70 (circa 1975), an instruction of the form ADD x(Rm),y(Rn) had a fetch/execute time of 1.35 microseconds plus source and destination times of 0.6 microseconds each, for a total instruction time of 2.55 microseconds. Any case where addressed memory was not in the cache added 1.02 microseconds. The register-to-register ADD Rm,Rn could execute from the cache in 0.3 microseconds. Floating point was even more complex, since there was some overlap between the CPU and the floating-point processor, but in general, floating point was significantly slower. A single-precision floating add instruction could range from 2.4 to 5.5 microseconds plus time to fetch the operands.[4]