Program status word

The program status word[lower-alpha 1] (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360[1] and its successors,[2][3][4][5][6] and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit.

Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.

Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.)

The 64-bit PSW describes (among other things)

In the early instances of the architecture (System/360 and early System/370), the instruction address was 24[lower-alpha 2] bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits.

In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits.

The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).

Format

S/360
IBM S/360 PSW formats
S/360 Standard PSW[11]

System Mask Key A M W P Interruption Code[12]
0 7 8 11 12 13 14 15 16 31

ILC CC Program
Mask		 Instruction Address
32 33 34 35 36 39 40 63
S/360 Standard PSW abbreviations
Bits Field Meaning
0-7 SM
System Mask
Bit Meaning
0 Channel 0 mask
1 Channel 1 mask
2 Channel 2 mask
3 Channel 3 mask
4 Channel 4 mask
5 Channel 5 mask
6 Channel 6 mask
7 External Mask
8-11 Key PSW key
12 A ASCII
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-31 IC Interruption Code[13]
32-33 ILC Instruction-Length Code[14]
34-35 CC Condition Code
36-39 PM
Program Mask
Bit Meaning
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
40-63 IA Instruction Address
S/360 Extended PSW[15]

spare 24/32
Bit
Mode		 Tran
Ctrl		 I/O
Mask		 Ext.
Mask		 Key A M W P ILC CC Program
Mask		 spare
0 3 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

Instruction Address
32 63
S/360 Extended PSW abbreviations
Bits Field Meaning
0-3 Spare (must be 0)
4 24/32-bit Address mode
5 Translation Control
6 IO I/O Mask (Summary)
7 EX External Mask (Summary)
8-11 Key Protection Key
12 A ASCII
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 ILC Instruction-Length Code[16]
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
24-31 Spare
32-63 IA Instruction Address

S/370
IBM S/370 PSW formats
S/370 Basic Control mode PSW[17]

Chan.
Mask		 I
O		 E
X		 Key 0 M W P Interruption Code
0 1 2 4 5 6 7 8 11 12 13 14 15 16 31

ILC CC Program
Mask		 Instruction Address
32 33 34 35 36 39 40 63
S/370 BC mode PSW abbreviations
Bits Field Meaning
0-5 Channel Masks for channels 0-5
6 IO I/O Mask for channels > 5
7 EX External Mask
8-11 Key PSW key
12 E=0 Basic Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-31 IC Interruption Code[18]
32-33 ILC Instruction-Length Code[19]
34-35 CC Condition Code
36-39 PM
Program Mask
Bit Meaning
36 Fixed-point overflow
37 Decimal overflow
38 Exponent underflow
39 Significance
40-63 IA Instruction Address
S/370 Extended Control mode PSW[20]

0 R 0 0 0 T I
O		 E
X		 Key 1 M W P S 0 CC Program
Mask		 0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

0 0 0 0 0 0 0 0 Instruction Address
32 39 40 63
S/370 EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16 S Address-Space Control
0=primary-space mode
1=Secondary-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
40-63 IA Instruction Address

S/370 Extended Architecture (S/370-XA)
IBM Extended Architecture (XA) PSW format
Extended Architecture Extended Control mode PSW[21]

0 R 0 0 0 T I
O		 E
X		 Key 1 M W P S 0 CC Program
Mask		 0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

A Instruction Address
32 33 63
S/370-XA EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16 S Address-Space Control
0=primary-space mode
1=Secondary-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow
23 Significance
32 A Addressing mode
0=24 bit; 1=31 bit
33-63 IA Instruction Address

Enterprise Systems Architecture (ESA)
IBM Enterprise Systems Architecture (ESA) PSW format
Enterprise Systems Architecture Extended Control mode PSW[22][23]

0 R 0 0 0 T I
O		 E
X		 Key 1 M W P AS CC Program
Mask		 0 0 0 0 0 0 0 0
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 31

A Instruction Address
32 33 63
ESA EC mode PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O Mask; subject to channel mask in CR2
7 EX External Mask; subject to external subclass mask in CR0
8-11 Key PSW key
12 E=1 Extended Control mode
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 Exponent underflow[lower-alpha 3]
23 Significance[lower-alpha 4]
32 A Addressing mode
0=24 bit; 1=31 bit
33-63 IA Instruction Address

z/Architecture
IBM z/Architecture PSW formats
z/Architecture long PSW[24]

0 R 0 0 0 T I
O		 E
X		 Key 0 M W P AS CC Program
Mask		 R
I		 0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 30 31

B
A		 0
32 33 63

Instruction Address
64 95

Instruction Address (Continued)
96 127
Long PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=0 Must be zero for LPSWE
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
64-127 IA Instruction Address
z/Architecture short PSW[25]

0 R 0 0 0 T I
O		 E
X		 Key 1 M W P AS CC Program
Mask		 R
I		 0 0 0 0 0 0 E
A
0 1 2 4 5 6 7 8 11 12 13 14 15 16 17 18 19 20 23 24 25 30 31

B
A		 Instruction Address
32 33 63
Short PSW abbreviations
Bits Field Meaning
1 R PER Mask
5 T DAT mode
6 IO I/O mask
7 EX External Mask
8-11 Key PSW key
12 E=1 Must be one for LPSW
13 M Machine-check mask
14 W Wait state
15 P Problem state
16-17 AS Address-Space Control
00=primary-space mode
01=Access-register mode
10=Secondary-space mode
11=Home-space mode
18-19 CC Condition Code
20-23 PM
Program Mask
Bit Meaning
20 Fixed-point overflow
21 Decimal overflow
22 HFP Exponent underflow
23 HFP Significance
24 RI Reserved for IBM
31 EA Extended Addressing mode
0=defined by BA below; 1=64-bit, BA must be zero
32 BA Basic Addressing mode
0=24 or 64; 1=31
33-63 IA Instruction Address

Notes
  1. The nomenclature varies among architectures.
  2. However, a 360/67[7] equipped with the Extended Dynamic Address Translation[8] feature has a 32-bit mode selected by bit 4 of the PSW[9] in Extended PSW mode[8] (Control Register 6, bit 8[10]).
  3. Bit 22 is renamed as HFP exponent underflow in ESA/390
  4. Bit 23 is renamed as HFP significance in ESA/390

References
  1. S360.
  2. S370.
  3. S370-XA.
  4. S370-ESA.
  5. S390-ESA.
  6. z.
  7. func67.
  8. func67, p. 57, Glossary.
  9. func67, p. 15, Instruction Fetching and Execution.
  10. func67, p. 16, Table 4. Control Registers.
  11. S360, p. 15, Program Status Word.
  12. S360, pp. 15-16, Interruption.
  13. S370, pp. 15-16, Interruption.
  14. S370, p. 156, Instruction-Length Code.
  15. func67, pp. 15-16, Instruction Fetching and Execution.
  16. S360, p. 156, Instruction-Length Code.
  17. S370, pp. 4-8 – 4-9, Program-Status Word Format in BC Mode.
  18. S370, pp. 6-3 – 6-5, Interruption Action.
  19. S370, pp. 6-7 – 6-9, Instruction-Length Code.
  20. S370, pp. 4-6 – 4-7, Program-Status Word Format in EC Mode.
  21. S370-XA, p. 4-5, Program-Status-Word Format.
  22. S370-ESA, p. 4-5, Program-Status-Word Format.
  23. S390-ESA, p. 4-5, Program-Status-Word Format.
  24. z, pp. 4-5 – 4-8, Program-Status-Word Format.
  25. z, p. 4-8, Short PSW Format.
S360
IBM System/360 Principles of Operation (PDF) (Eighth ed.). IBM. September 1968. A22-6821-7.
func67
IBM System/360 Model 67 Functional Characteristics (PDF) (Third ed.). IBM. February 1972. GA27-2719-2.
S370
IBM System/370 Principles of Operation (PDF) (Eleventh ed.). IBM. September 1987. A22-7000-10.
S370-XA
IBM System/370 Extended Architecture Principles of Operation (PDF) (Second ed.). IBM. January 1987. SA22-7085-1.
S370-ESA
IBM Enterprise Systems Architecture/370 Principles of Operation (PDF) (First ed.). IBM. August 1988. SA22-7200-0.
z
z/Architecture Principles of Operation (PDF) (Thirteenth ed.). IBM. September 2019. SA22-7832-12.


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