SGI Challenge

SGI Power Challenger GR

The POWER Challenge was announced on 28 January 1993[1] and was intended to compete against supercomputer companies such as Cray Research.[1] At the time of its announcement, Silicon Graphics claimed that the POWER Challenge would have the same level of performance as Cray's Cray Y-MP with a single microprocessor.[1] The new model was introduced in the middle of 1994 and used the MIPS R8000 microprocessor chip set, which consisted of the R8000 microprocessor and R8010 floating point unit accompanied by a "streaming" cache and its associated controllers. Much of the POWER Challenge's performance depended on the R8000, a microprocessor intended to achieve supercomputing performance and designed for floating-point scientific applications.[2] As a result, the R8000 had features such as fused multiply–add instructions and a large cache.[2]

In 1995, Silicon Graphics upgraded the POWER Challenge with R8000 microprocessors clocked at 90 MHz, enabling the system to scale up to 6.48 GFLOPS, an improvement of 1 GFLOPS over the previous R8000 microprocessor clocked at 75 MHz.

The POWER Challenge 10000 referred to POWER Challenge-based systems that used the R10000 microprocessor. These models were introduced in January 1996, succeeding the R4400-based Challenge and the R8000-based POWER Challenge, although such systems co-existed with the POWER Challenge 10000 for some time. To support the new R10000s, a new CPU board, the "IP25" was introduced. The new CPU board, like previous IP19 CPU board, support four processors each and their associated secondary caches.

The CHALLENGEarray and POWER CHALLENGEarray is a cluster of Challenge or POWER Challenge servers respectively. The CHALLENGEarray supports 2 to 288 R10000 processors while the POWER CHALLENGEarray supports 2 to 144 R8000 processors and up to 128 GB of memory. The POWER CHALLENGEarray was introduced on 15 November 1994.

Other systems from Silicon Graphics that used the "Challenge" brand were the Challenge M and the Challenge S. These systems were repackaged Silicon Graphics Indigo2 and Indy workstations that were not configured with the graphics hardware that made them useful as workstations. These systems were Challenges in name only and have no architectural similarity with the multiprocessing Challenges, although they had cases with the same blue hue as proper Challenges. They were branded as such in order for the systems to be marketed as part of the Challenge server family, positioned as entry level servers.

The Challenge uses a board set known as the POWERpath-2 board set, code named "Everest". The boards that make up this board set are the IP19, IP21, IP25 CPU boards, the MC3 memory board and the IO4 POWERchannel-2 interface board.

The CPU board contains the microprocessors. There are three models of CPU boards, the IP19, IP21 and IP25. The IP19 can be configured with two or four R4400 microprocessors. It also contains five CPU Interface ASICs, four for implementing the data path and one for implementing the address path. These ASICs contain an average of 80,000 gates each.[5] The IP21 supports the R8000 microprocessor and can be configured with one or two such microprocessors. The IP25 supported R10000 microprocessors.

Memory is provided by the MC3 memory board, which contains thirty-two single in-line memory module (SIMM) slots and two leaf controllers. Fast page mode (FPM) error correcting code (ECC) SIMMs with capacities of 16 MB (known as the "high-density" SIMM) and 64 MB (known as the "super-density" SIMM) are supported, enables the board to provide 64 MB to 2 GB of memory. The SIMMs are installed in groups of four.

The memory is organized into eight banks, with four banks forming a leaf. The memory can be interleaved if there are two or more leaves present in the system. The memory bus is 576-bit wide, with a 512-bit path for data and a 64-bit path for ECC. The memory is controlled by the two leaf controllers. Each leaf controller manages four banks of memory and half of a memory transaction. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.[6]

Memory transactions are 128-byte wide, the same width as the cache line of the MIPS microprocessors used. A memory read is completed in two cycles of the memory clock, and is buffered by the leaf controllers before it is placed in a sent over the POWERpath-2 bus in four cycles of the POWERpath-2 bus clock.[6]

The SIMMs are protected by ECC, and the ECC implementation can correct single-bit errors and detect double-bit errors. The SIMMs also contain built-in self-test circuitry, which tests the SIMM during power on or reset and alerts the firmware, which disables the bank(s) of memory containing faulty SIMM(s), if faults are detected.[6]