STM8

The STM8 is an 8-bit microcontroller family by STMicroelectronics. The STM8 microcontrollers use an extended variant of the ST7 microcontroller architecture. STM8 microcontrollers are particularly low cost for a full-featured 8-bit microcontroller.[1]

Architecture

The STM8 is very similar to the earlier ST7, but is better suited as a target for C due to its 16-bit index registers and stack pointer-relative addressing mode. Although internally a Harvard architecture it has a unified 24-bit address space, allowing code to execute out of RAM (useful for in-system programming of the flash ROM), and data (such as lookup tables) to be accessed out of ROM. Access to data above 64K is limited to special "load far" instructions; most operations' memory operands can access at most 128K (a 16-bit base address plus 16-bit offset).

Very few STM8 microcontrollers have more than 64K of data memory.

It has the same six registers (A, X, Y, SP, PC, CC) as the ST7, but the index registers X and Y have been expanded to 16 bits, and the program counter has been expanded to 24 bits. The accumulator A and the stack pointer remain 8 and 16 bits, respectively.[2]

The condition code register has two more defined bits, for a total of seven. There is an overflow flag, and a second interrupt enable bit, allowing four interrupt priority levels.

Subfamilies

  • STM8AF automobile
  • STM8AL automobile low-power
  • STM8L low-power
  • STM8S low-cost
  • STM8T touch-sensing
  • STLUX lighting control
  • STNRG Pulse-width modulation-controllers

Compiler support

The STM8 is supported by the free Small Device C Compiler, the free of charge closed source Cosmic C compiler,[3] and the non-free IAR C and Raisonance compilers. Besides C there is STM8 eForth, an open source port of the Forth programming language.

Changes compared to ST7

The STM8 instruction set is mostly a superset of the ST7's, but it is not completely binary compatible.

Operations on the X and Y registers are extended to 16 bits. Thus, loads and stores access two bytes of memory rather than one. (Also, the half-carry flag has been changed to reflect the carry from bit 7 to bit 8 of the 16-bit result, rather than the carry from bit 3 to 4.)

Interrupts push nine bytes of state instead of five on the ST7.

The multiply instruction stores the 16-bit product in the specified index register (e.g. X), rather than dividing it between X and A.

Indirect addressing modes which fetch an 8-bit address from memory (opcodes 92 2x, 92 3x, 92 Bx, 92 6x, 92 Ex, 91 6x, and 91 Ex) have been deleted; all indirect addressing modes fetch 16-bit addresses. A new prefix byte 72 has been added, and used to encode indirect starting with a 16-bit address.

The bit manipulation instructions have been changed to take a 16-bit address and to require the 72 prefix byte. The unprefixed opcodes 0x and 1x they formerly occupied are instead used for stack-pointer relative addressing.

Some rarely used branch instructions have had their opcodes changed to require a 90 prefix, and the unprefixed opcodes reassigned to signed branches which depend on the V flag.

Load and compare instructions targeting the X register are of little use on the ST7 with addressing modes indexed by the X register. On the STM8, when such operations specify a memory operand indexed by the X register, the register operand is changed to Y. With a 90 prefix, the registers are reversed so the index register is Y and the operand register is X.

One major performance difference is that the STM8 fetches 32 bits from ROM per cycle, and typical instructions take one cycle to execute plus one cycle per RAM access. The ST7, in contrast, fetches 8 bits per cycle and takes one cycle per instruction byte.

Instruction set

STM8 instructions consist of an optional prefix byte (7216, 9016, 9116, or 9216), an opcode byte, and a few (up to four, but rarely more than two) bytes of operands. Prefix bytes mostly modify the addressing mode used to specify the memory operand, but in some cases, prefixes 72 and 90 perform a different operation entirely.

Prefix 90 exchanges X and Y in the following instruction. In the table below, these variants are combined on one line by writing "X/Y", which means either "X" or "Y". Prefix 90 is also used in two places to introduce new opcodes: the BCPL and BCCM instructions, and some branch conditions.

Prefix 92 converts instructions with an offset operand (addr16,X) to indirect addressing ([addr8],X). The offset is replaced by the 8-bit address of a 16-bit offset value in memory. It is used only for this function.

Prefix 91 has both of the preceding effects, converting (addr16,X) addressing modes to ([addr8],Y).

Prefix 72 is used in a number of places, in a much less regular pattern. In some cases, it introduces new addressing modes (particularly an ([addr16],X) 16-bit indirect mode), but it also introduces many completely new operations.

STM8 instruction set[2]
Prefix76543210OperandsMnemonicDescription
0000opcodeaddr8OP (addr8,SP)One-operand instructions (see below)
0001opcodeaddr8OP A,(addr8,SP)Two-operand instructions with stack operand
00010000addr8SUB A,(addr8,SP)A := A − operand
00010001addr8CP A,(addr8,SP)Compare A − operand
00010010addr8SBC A,(addr8,SP)A := A − operand − C subtract with borrow
—/9000010011addr8CPW X/Y,(addr8,SP)Compare X/Y − operand (16-bit)
00010100addr8AND A,(addr8,SP)A := A & operand, bitwise and
00010101addr8BCP A,(addr8,SP)Bitwise test A & operand
00010110addr8LDW Y,(addr8,SP)Y := operand (LD A,(addr8,SP) assigned to opcode 7B)
00010111addr8LDW (addr8,SP),YOperand := Y (LD (addr8,SP),A assigned to opcode 6B)
00011000addr8XOR A,(addr8,SP)A := A ^ operand, exclusive-or
00011001addr8ADC A,(addr8,SP)A := A + operand + C, add with carry
00011010addr8OR A,(addr8,SP)A := A | operand, inclusive or
00011011addr8ADD A,(addr8,SP)A := A + operand
00011100imm16ADDW X,#imm16X := X + immediate (=JP (addr8,SP))
00011101imm16SUBW X,#imm16X := X − immediate (=CALL (addr8,SP))
00011110addr8LDW X,(addr8,SP)X := operand
00011111addr8LDW (addr8,SP),XOperand := X
72/90000cbitvoperandsBit operations
720000bit0addr16 soff8BTJT addr16,#bit,labelJump to PC + soff8 if source bit is true (set)
720000bit1addr16 soff8BTJF addr16,#bit,labelJump to PC + soff8 if source bit is false (clear)
720001bit0addr16BSET addr16,#bitSet specified bit to 1
720001bit1addr16BRES addr16,#bitReset (clear) specified bit to 0
900001bit0addr16BCPL addr16,#bitComplement (toggle) selected bit
900001bit1addr16BCCM addr16,#bitWrite carry flag to memory bit
—/900010conditionsoff8Conditional branches (8-bit signed offset)
00100000soff8JRA labelBranch always (true)
00100001soff8JRF labelBranch never (false)
00100010soff8JRUGT labelBranch if unsigned greater than (C=0 and Z=0)
00100011soff8JRULE labelBranch if unsigned less than or equal (C=1 or Z=1)
00100100soff8JRNC labelBranch if no carry (C=0)
00100101soff8JRC labelBranch if carry (C=1)
00100110soff8JRNE labelBranch if not equal (Z=0)
00100111soff8JREQ labelBranch if equal (Z=1)
00101000soff8JRNV labelBranch if not overflow (V=0)
9000101000soff8JRNH labelBranch if not half-carry (H=0)
00101001soff8JRV labelBranch if overflow (V=1)
9000101001soff8JRH labelBranch if half-carry (H=1)
00101010soff8JRPL labelBranch if plus (N=0)
00101011soff8JRMI labelBranch if minus (N=1)
00101100soff8JRSGT labelBranch if signed greater than (S=0 and N=V)
9000101100soff8JRNM labelBranch if not interrupt mask (I=0)
00101101soff8JRSLE labelBranch if signed lower or equal (S=1 or N≠V)
9000101101soff8JRM labelBranch if interrupts masked (I=1)
00101110soff8JRSGE labelBranch if signed greater or equal (N=V)
9000101110soff8JRIL labelBranch if interrupt line is low
00101111soff8JRSLT labelBranch if signed less than (N≠V)
9000101111soff8JRIH labelBranch if interrupt line is high
prefix0modeopcodeoperandOne-operand instructions
0000opcodeaddr8OP (addr8,SP)Stack pointer relative
0011opcodeaddr8OP addr88-bit absolute address
720011opcodeaddr16OP [addr16]16-bit indirect address
920011opcodeaddr8OP [addr8]8-bit indirect address of 16-bit address
0100opcodeOP AAccumulator
72/900100opcodeaddr16OP (addr16,X/Y)Indexed with 16-bit offset
—/900101opcodeOPW X/YX/Y register (16-bit operation)
720101opcodeaddr16OP addr1616-bit address
—/900110opcodeaddr8OP (addr8,X/Y)8-bit address plus X/Y
720110opcodeaddr16OP ([addr16],X)16-bit indirect address plus X
92/910110opcodeaddr8OP ([addr8],X/Y)8-bit indirect address plus X/Y
—/900111opcodeOP (X/Y)Indexed with no offset
prefix0mode0000operandNEG operandTwo's-complement negate
0mode0001(reassigned to exchange operations; see following section)
0mode0010(reassigned to other operations; see following section)
prefix0mode0011operandCPL operandOnes' complement, logical not
prefix0mode0100operandSRL operandShift right logical, msbit cleared, lsbit to carry: (operand:C) := (0:operand)
0mode0101(reassigned to other operations; see following section)
prefix0mode0110operandRRC operandRotate right through carry, (operand:C) := (C:operand)
prefix0mode0111operandSRA operandShift right arithmetic, msbit preserved, lsbit to carry
prefix0mode1000operandSLL operandShift left, msbit to carry: (C:operand) := (operand:0)
prefix0mode1001operandRLC operandRotate left through carry, (C:operand) := (operand,C)
prefix0mode1010operandDEC operandDecrement; N and Z set, carry unaffected
0mode1011(reassigned to other operations; see following section)
prefix0mode1100operandINC operandIncrement; N and Z set, carry unaffected
prefix0mode1101operandTNZ operandTest non-zero: set N and Z based on operand value
prefix0mode1110operandSWAP operandSwap halves of operand (4-bit rotate; 8-bit for SWAPW X and SWAPW Y)
prefix0mode1111operandCLR operandSet operand to 0, N cleared, Z set
prefix0modeopcodeoperandReassigned opodes [03-7][125B] from one-operand range
—/9000000001RRWA X/YRotate word right through A: 8-bit right rotate of 24-bit concatenation of X/Y and A; (X:A) := (A:X)
00110001addr16EXG A,addr16Exchange A with memory
01000001EXG A,XLExchange A with X (low half)
01010001EXGW X,YExchange X with Y (16 bits)
01100001EXG A,YLExchange A with Y (low half)
01110001(reserved)
—/9000000010RLWA X/YRotate word left through A: 8-bit left rotate of 24-bit concatenation of X/Y and A; (A:X) := (X:A)
00110010addr16POP addr16Pop from stack
—/9001000010MUL X/Y,AX/Y := XL/YL × A
01010010imm8SUBW SP,#immSP := SP − imm8
—/9001100010DIV X/Y,ADivide X/Y by A; 16-bit quotient in X/Y, remainder in A
01110010PREFIXInstruction prefix 72: modify following opcode
00000101(reserved)
00110101imm8 addr16MOV addr16,#imm8Move immediate to memory (flags unaffected)
01000101addr8 addr8MOV addr8,addr8Move memory to memory (flags unaffected)
01010101addr16 addr16MOV addr16,addr16Move memory to memory (flags unaffected)
01100101DIVW X,YDivide X by Y (16 bits); quotient in X, remainder in Y
01110101(reserved)
00001011(reserved)
00111011addr16PUSH addr16Push onto stack
01001011imm8PUSH #imm8Push onto stack
01011011imm8ADDW SP,#imm8SP := SP + imm8
01101011addr8LD (addr8,SP),AStore relative to stack
01111011addr8LD A,(addr8,SP)Load relative to stack
100opcodeMiscellaneous instructions. None implicitly set the condition codes.
10000000IRETReturn from interrupt (pop CC, A, X, Y, PC)
10000001RETPop 16-bit return address from stack to PC
10000010addr24INTSpecial jump for interrupt vector table
10000011TRAPForce trap interrupt
10000100POP APop A from stack
—/9010000101POPW X/YPop X/Y from stack (16 bits)
10000110POP CCPop condition codes from stack
10000111RETFPop 24-bit return address from stack to PC
10001000PUSH APush A onto stack
—/9010001001PUSHW X/YPush X/Y onto stack (16 bits)
10001010PUSH CCPush condition codes onto stack
10001011BREAKStop for debugger if present, or NOP
10001100CCFComplement (toggle) carry flag
10001101addr24CALLF addr24Push 24-bit PC; PC := addr24
9210001101addr16CALLF [addr16]Indirect far call; address is of 24-bit pointer
10001110HALTHalt processor and clocks
10001111WFIWait for interrupt, halting processor but not clocks
7210001111WFEWait for event (coprocessor), handling interrupts normally while waiting
10010000PDYInstruction prefix 90: swap X and Y in next instruction
10010001PIYInstruction prefix 91: PDY plus PIX
10010010PIXInstruction prefix 92: use 8-bit memory indirect for operand
—/9010010011LDW X/Y,Y/XX/Y := Y/X
—/9010010100LDW SP,X/YSP := X/Y
—/9010010101LD XH/YH,AXH/YH := A
—/9010010110LDW X/Y,SPX/Y := SP
—/9010010111LD XL/YL,AXL/YL := A
10011000RCFReset (clear) carry flag
10011001SCFSet carry flag
10011010RIMReset interrupt mask (enable interrupts)
10011011SIMSet interrupt mask (disable interrupts)
10011100RVFReset (clear) overflow flag
10011101NOPNo operation
—/9010011110LD A,XH/YHA := XH/YH
—/9010011111LD A,XL/YLA := XL/YL
Prefix1modeopcodeoperandTwo-operand instructions A := A op operand
0001opcodeaddr8OP (addr8,SP)Stack-relative operand (see above; opcodes 16, 17, 1C, 1D do not follow pattern)
1010opcodeimm8OP #imm88-bit immediate operand (forbidden as destination)
1011opcodeaddr8OP addr88-bit absolute address (forbidden for jump/call)
1100opcodeaddr16OP addr1616-bit absolute address
721100opcodeaddr16OP [addr16]16-bit indirect address
921100opcodeaddr8OP [addr8]8-bit indirect address of 16-bit address
—/901101opcodeaddr16OP (addr16,X/Y)Indexed with 16-bit offset
721101opcodeaddr16OP ([addr16],X)16-bit indirect + X
92/911101opcodeaddr16OP ([addr8],X/Y)8-bit indirect + X/Y
—/901110opcodeaddr8OP (addr8,X/Y)Indexed with 8-bit offset
—/901111opcodeOP (X/Y)Indexed with no offset
prefix1mode0000operandSUB A,operandA := A − operand
prefix1mode0001operandCP A,operandCompare A − operand
prefix1mode0010operandSBC A,operandA := A − operand − C subtract with borrow
prefix1mode0011operandCPW X/Y,operandCompare X/Y − operand (16 bit); compare Y/X if operand mode is indexed by X/Y (opcodes D3, E3, F3)
prefix1mode0100operandAND A,operandA := A & operand, bitwise and
prefix1mode0101operandBCP A,operandBitwise test A & operand
prefix1mode0110operandLD A,operandA := operand
prefix1mode0111operandLD operand,AOperand := A (mode 2 LD #imm8,A reassigned, see below)
prefix1mode1000operandXOR A,operandA := A ^ operand, exclusive-or
prefix1mode1001operandADC A,operandA := A + operand + C, add with carry
prefix1mode1010operandOR A,operandA := A | operand, inclusive or
prefix1mode1011operandADD A,operandA := A + operand
prefix1mode1100operandJP operandLow 16 bits of PC := operand, unconditional jump (modes 2 JP #imm8 and 3 JP addr8 reassigned, see below)
prefix1mode1101operandCALL operandPush 16-bit PC, low 16 bits of PC := operand (modes 2 CALL #imm8 and 3 CALL addr8 reassigned, see below)
prefix1mode1110operandLDW X/Y,operandLoad X/Y := operand; use 16 instead of 90 1E for LDW Y,(addr8,SP)
prefix1mode1111operandLDW operand,X/YOperand := X/Y (16-bit, mode 2 LD #imm8,X reassigned, see below); store Y/X if operand mode is indexed by X/Y (opcodes DF, EF, FF); use 17 instead of 90 1F for LDW (addr8,SP),Y
Prefix1modeopcodeoperandReassigned opcodes A7, AC, BC, AD, BD, AF from two-operand range
—/9010100111addr24LDF (addr24,X/Y),ALoad far (=LD #imm8,A)
92/9110100111addr16LDF ([addr16],X/Y),A16-bit address of 24-bit pointer
10101100addr24JPF addr24PC := addr24 (=JP #imm8)
9210101100addr16JPF [addr16]Indirect far jump; address is of 24-bit pointer
10111100addr24LDF A,addr24Load far (=JP addr8)
9210111100addr16LDF A,[addr16]Load far, 16-bit address of 24-bit pointer
10101101soff8CALLR labelPush 16-bit PC, PC := PC + operand (=CALL #imm8)
10111101addr24LDF addr24,AOperand := A (=CALL addr8)
9210111101addr16LDF [addr16],AOperand := A, 16-bit address of 24-bit pointer
—/9010101111addr24LDF A,(addr24,X/Y)Load far (=LDW #imm8,X)
92/9110101111addr16LDF A,([addr16],X/Y)16-bit address of 24-bit pointer
721modeopcodeoperandIndex register arithmetic (16-bit) X/Y := X/Y ± operand
721010opcodeimm16OPW X/Y,#imm1616-bit immediate
721011opcodeaddr16OPW X/Y,addr1616-bit absolute
721111opcodeaddr8OPW X/Y,(addr8,SP)Stack-relative
721mode0000operandSUBW X,operandX := X − operand (prefer opcode 1D for SUBW X,#imm16)
721mode0010operandSUBW Y,operandY := Y − operand
721mode1001operandADDW Y,operandY := Y + operand
721mode1011operandADDW X,operandX := X + operand (prefer opcode 1C for ADDW X,#imm16)

For CPW and LDW instructions where the operand addressing mode is indexed by X, the STM8 uses the Y register by default instead of X. Applying a 90 prefix exchanges X and Y so the register is X and the addressing mode is indexed by Y.

References

  1. Carlson, Jay (September 15, 2017). "ST STM8". Retrieved 2018-06-12.
  2. "PM0044: STM8 CPU programming manual" (PDF). STMicroelectronics. September 2011. Document 13590 Rev 3. Retrieved 2018-06-10.
  3. "COS-C-COMPILER - Free C Compiler for all STM8, from Cosmic" (Press release). STMicroelectronics. Retrieved 24 March 2016.
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