Specman

Specman is an EDA tool that provides advanced automated functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.

The Specman tool itself does not include an HDL-simulator (for design languages such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. Specman is a feature of Cadence new Xcelium simulator, where tighter product integration offers both faster runtime performance and debug capabilities not available with other HDL-simulators. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Synopsys's VCS, or Mentor's Questa.