Cadence Design Systems

Cadence Design Systems began as an electronic design automation (EDA) company, formed by the 1988 merger of Solomon Design Automation (SDA), co-founded in 1983 by Richard Newton, Alberto Sangiovanni-Vincentelli and James Solomon, and ECAD, a public company co-founded by Glen Antle and Paul Huang in 1982. SDA's CEO Joseph Costello was appointed as CEO of the newly combined company.[3]

Following the resignation of Cadence's original CEO Joe Costello in 1997, Jack Harding was appointed CEO.[4] Ray Bingham was named CEO in 1999.[5] In 2004, Mike Fister became Cadence's new CEO.[6]

In 2008, Cadence's board appointed Lip-Bu Tan as acting CEO, after the resignation of Mike Fister; Tan had served on the Cadence Board of Directors since 2004.[7] In January 2009, the Cadence's board of directors voted unanimously to confirm Lip-Bu Tan as President and CEO. Tan had been most recently CEO of Walden International, a venture capital firm, where he remains chairman of the firm. [8] In 2017, Cadence appointed Anirudh Devgan as president, reporting to Lip-Bu Tan.[9]

• Virtuoso Platform. Tools for designing full-custom integrated circuits;[12] includes schematic entry, behavioral modeling (Verilog-AMS), circuit simulation, custom layout, physical verification, extraction and back-annotation. Used mainly for analog, mixed-signal, RF, and standard-cell designs, but also memory and FPGA designs.

• Spectre X. In June 2019, Cadence introduced Spectre X parallel circuit simulator, so that users could distribute time- and frequency-domain simulations across hundreds of CPUs for faster runtime and speed.[13]

• Genus, Innovus, Tempus & Voltus. In March 2020, Cadence announced that its Innovus place and route engine and optimizer were now integrated into the Genus Synthesis, with both tools using a using a common user interface and database;[14] Additionally, machine learning capabilities were introduced to target better performance power and area across the Innovus, Tempus Timing Sign-off, and Voltus IC Power Integrity digital flow.[15]

Other Cadence RTL to GDS II tools: Conformal Equivalence Checker, Stratus High-Level Synthesis, Joules Power Analysis, Quantus RC Extraction, Modus AutomaticTest Pattern Generation.

• Xcelium. Xcelium is a parallel simulator, introduced in 2017, based on a multi-core parallel computing architecture.[16]

• JasperGold. JasperGold is a formal verification tool, initially introduced in 2003.[17] In 2019, Cadence announced new machine learning technology to automate JasperGold solver selection and parameterization to achieve faster first-time proofs; additionally to optimize regression runs.[18]

• Perspec System Verifier. Perspec was announced in 2014, for defining and verifying system-level verification scenarios, and then creating test cases to verify the scenarios using constraint-solving technology.[19] In mid-2018, Cadence announced that Perspec supported the new Accellera Portable Test and Stimulus Standard (PSS) standard[20]

• vManager. In 2014, Cadence announced vManager, a verification management tool for tracking verification process, including coverage, using emulation, simulation and/or formal technology as the data source(s).[21]

• Palladium Z1. In 2015, Cadence announced the Palladium Z1 Hardware emulation platform,[22] with over 100 million gates per hour compile speed, and greater than 1MHz execution for billion-gate designs.[23] Cadence's Palladium emulator was originally from Cadence's Quickturn acquisition in 1998.[24]

• Protium S1/X1. FPGA prototyping platform was officially introduced in 2014.[25] In 2017, Cadence introduced the Protium S1 built on Xilinx Virtex UltraScale FPGAs.[26] In 2019, Protium X1 rack-based prototyping was introduced,[27] which Cadence claimed supported a 1.2 billion gate SoCs at around 5MHz.[28] Palladium S1/X1 and Protium share a single compilation flow.[29]

Design IP targeting areas including memory / storage / high-performance interface protocols (USB or PCIe controllers and PHYs), Tensilica DSP processors for audio, vision, wireless modems and convolutional neural nets. Tensilica DSP processors IP[30] include:

• Tensilica Vision DSPs for Imaging, Vision and AI processing[31][32]

• Tensilica HiFi DSPs for Audio/Voice/Speech processing[33][34]

• Tensilica Fusion DSPs for IoT[35]

• Tensilica ConnX DSPs for Radar, Lidar, and Communications processing[36][37]

• Tensilica DNA Processor Family for AI acceleration[38][39]

• Allegro Platform. Tools for co-design of integrated circuits, packages, and PCBs,[40] including the Specctra auto-router.

• OrCAD/PSpice. Tools for smaller design teams and individual PCB designers.[40]
• Sigrity. Tools for signal, power integrity and thermal integrity analysis and IC package design.[41]

• Clarity. Cadence introduced Clarity in April 2019, as part of its expansion into system analysis. Clarity is a 3D field solver for electromagnetic analysis, that uses distributed adaptive meshing to partition jobs across on hundreds of cores for gains in speed and capacity.[42]

• Celsius. In September 2019, Cadence announced Celsius, a parallel architecture thermal solver that uses finite element analysis for solid structures and computational fluid dynamics (CFD) for fluids.[43]

The company has also acquired High-Level Design (HLD), UniCAD, CadMOS, Ambit Design Systems, Simplex, Silicon Perspective, Plato, and Get2Chip.

• In 2007, Cadence was rumored to be in talks with Kohlberg Kravis Roberts and Blackstone Group regarding a possible sale of the company.[88]
• In 2008, Cadence withdrew a $1.6 billion offer to purchase rival Mentor Graphics.[89]

From 1995 till 2002, Cadence was involved in a 6-year-long legal dispute[90] with Avanti Corporation (brand name "Avant!"), in which Cadence claimed Avanti stole Cadence code, and Avanti denied it. According to Business Week "The Avanti case is probably the most dramatic tale of white-collar crime in the history of Silicon Valley".[90] The Avanti executives eventually pleaded no contest and Cadence received several hundred million dollars in restitution. Avanti was then purchased by Synopsys, which paid $265 million more to settle the remaining claims.[91] The case resulted in a number of legal precedents.[92]

Quickturn Design Systems, a company acquired by Cadence, was involved in a series of legal events with Aptix Corporation. Aptix licensed a patent to Mentor Graphics and the two companies jointly sued Quickturn over an alleged patent infringement. Amr Mohsen, CEO of Aptix, forged and tampered with legal evidence and was subsequently charged with conspiracy, perjury, and obstruction of justice. Mohsen was arrested after violating his bail agreement by attempting to flee the country. While in jail, Mohsen plotted to intimidate witnesses and kill the federal judge presiding over his case.[93] Mohsen was further charged with attempting to delay a federal trial by feigning incompetency.[94][95] Due to the overwhelming misconduct, the judge ruled the lawsuit as unenforceable and Mohsen was sentenced to 17 years in prison.[96] Mentor Graphics subsequently sued Aptix to recoup legal costs. Cadence also sued Mentor Graphics and Aptix to recover legal costs.[97]

In 2013, Cadence sued Berkeley Design Automation (BDA) for circumvention of a license scheme to link its Analog FastSpice (AFS) simulator to Cadence's Analog Design Environment (Virtuoso ADE).[98] The lawsuit was settled less than one year later with an undisclosed payment of BDA and a multi-year agreement to support interoperability of AFS with ADE through Cadence’s official interface. BDA was bought by Mentor Graphics a few months later.[99]