ZPU (microprocessor)

Many electronic projects include electronic logic in an FPGA. It's wasteful to also have a microprocessor, so it is commonplace to add a CPU to the electronic logic in the FPGA. Often, a smaller, less-expensive FPGA could be used if only the CPU used less resources. This is the exact situation that the ZPU was designed to address.

The ZPU is designed to handle the miscellaneous tasks of a system that are best handled by software, for example, a user interface. The ZPU is very slow, but its small size helps to place any needed high-speed algorithm in the FPGA.

Another issue is that most CPUs for FPGAs are closed-source, available only from a particular maker of FPGAs. Occasionally a project needs to have a design that can be widely distributed, for security inspections, educational uses or other reasons. The licenses on these proprietary CPUs can prevent these uses. The ZPU is open-sourced.

Some projects need code that must be small, but run on a CPU that inherently has larger code. Alternatively, a project may benefit from the wide selection of code, compilers and debugging tools for the GNU Compiler Collection. In these cases, an emulator can be written to implement the ZPU's instruction set on the target CPU, and the ZPU's compilers can be used to produce the code. The resulting system is slow, but packs code into less memory than many CPUs and enables the project to use a wide variety of compilers and code.[4]

The ZPU was designed explicitly to minimize the amount of electronic logic. It has a minimal instruction set, yet can be encoded for the GNU Compiler Collection. It also minimizes the number of registers that must be in the FPGA, minimizing the number of flip-flops. Instead of registers, intermediate results are kept on the stack, in memory.[1]

It also has small code, saving on memory. Stack machine instructions do not need to contain register IDs, so the ZPU's code is smaller than other RISC CPUs, said to need only about 80% of the space of ARM Holdings Thumb2.[1] For example, the signed immediate helps the ZPU store a 32-bit value in at most 5 bytes of instruction space, and as little as one. Most RISC CPUs require at least eight bytes.

Finally, about 2/3 of its instructions can be emulated by firmware implemented using the other 1/3 "required" instructions. Although the result is very slow, the resulting CPU can require as little as 446 lookup-tables (a measure of FPGA complexity, roughly equivalent to 1700 electronic logic gates).

The ZPU has a reset vector, consisting of 32-bytes of code space starting at location zero. It also has a single edge-sensitive interrupt, with a vector consisting of 32 bytes of code space beginning at address 32. Vectors 2 through 63 each have 32 bytes of space, but are reserved for code to emulate instructions 33 through 63.

The base ZPU has a 32-bit data path. The ZPU also has a variant with a 16-bit-wide data path, to save even more logic.

The ZPU has a well-tested port of the GNU Compiler Collection.[1] Enthusiasts and firmware engineers have ported ECos,[1] FreeRTOS[5] and μClinux.[6] At least one group of enthusiasts have copied the popular development environment of the Arduino and adapted it to the ZPU.[7]

There are now multiple models of the ZPU core. Besides the original Zylin cores,[1] there are also the ZPUino cores,[7] and the ZPUFlex core.[8] The Zylin core is designed for a minimal FPGA footprint, and includes a 16-bit version. The ZPUino has practical improvements for speed, can replace emulated instructions with hardware, and is embedded in a system-on-chip framework. The ZPUFlex is designed to use external memory blocks and can replace emulated instructions with hardware.

Academic projects include power efficiency studies and improvements,[9] and reliability studies.[10]

To improve speed, most implementors have implemented the emulated instructions, and added a stack cache.[7][8][9] Beyond this, one implementor said that a two-stack architecture would permit pipelining (i.e. improving speed to one instruction per clock cycle), but this might also require compiler changes.[9]

One implementor reduced power usage by 46% with a stack cache and automated insertion of clock gating.[9] The power usage was then roughly equivalent to the small open-source Amber core, which implements the ARM v2a architecture.

The parts of the ZPU that would be most aided by fault-tolerance are the address bus, stack pointer and program counter.[10]

"TOS" is an abbreviation of the "Top Of Stack." "NOS" is an abbreviation of the "Next to the top Of Stack."

Code points 33 to 63 may be emulated by code in vectors 2 through 32: LOADH and STOREH (16-bit memory access), LESSTHAN (comparisons set 1 for true, 0 for false), LESSTHANOREQUAL, ULESSTHAN, ULESSTHANOREQUAL, SWAP (TOS with NOS), MULT, LSHIFTRIGHT, ASHIFTLEFT, ASHIFTRIGHT, CALL, EQ, NEQ, NEG, SUB, XOR, LOADB and STOREB (8-bit memory access), DIV, MOD, EQBRANCH, NEQBRANCH, POPPCREL, CONFIG, PUSHPC, SYSCALL, PUSHSPADD, HALFMULT, CALLPCREL