Ceramic capacitor

Class 1 ceramic capacitors are accurate, temperature-compensating capacitors. They offer the most stable voltage, temperature, and to some extent, frequency. They have the lowest losses and therefore are especially suited for resonant circuit applications where stability is essential or where a precisely defined temperature coefficient is required, for example in compensating temperature effects for a circuit. The basic materials of class 1 ceramic capacitors are composed of a mixture of finely ground granules of paraelectric materials such as Titanium dioxide (TiO
₂), modified by additives of Zinc, Zirconium, Niobium, Magnesium, Tantalum, Cobalt and Strontium, which are necessary to achieve the capacitor's desired linear characteristics.[9][10]

The general capacitance temperature behavior of class 1 capacitors depends on the basic paraelectric material, for example TiO
₂. The additives of the chemical composition are used to adjust precisely the desired temperature characteristic. Class 1 ceramic capacitors have the lowest volumetric efficiency among ceramic capacitors. This is the result of the relatively low permittivity (6 to 200) of the paraelectric materials. Therefore, class 1 capacitors have capacitance values in the lower range.

Class 1 capacitors have a temperature coefficient that is typically fairly linear with temperature. These capacitors have very low electrical losses with a dissipation factor of approximately 0.15%. They undergo no significant aging processes and the capacitance value is nearly independent of the applied voltage. These characteristics allow applications for high Q filters, in resonant circuits and oscillators (for example, in phase-locked loop circuits).

The EIA RS-198 standard codes ceramic class 1 capacitors with a three character code that indicates temperature coefficient. The first letter gives the significant figure of the change in capacitance over temperature (temperature coefficient α) in ppm/K. The second character gives the multiplier of the temperature coefficient. The third letter gives the maximum tolerance from that in ppm/K. All ratings are from 25 to 85 °C:

In addition to the EIA code, the temperature coefficient of the capacitance dependence of class 1 ceramic capacitors is commonly expressed in ceramic names like "NP0", "N220" etc. These names include the temperature coefficient (α). In the IEC/EN 60384-8/21 standard, the temperature coefficient and tolerance are replaced by a two digit letter code (see table) in which the corresponding EIA code is added.

For instance, an "NP0" capacitor with EIA code "C0G" will have 0 drift, with a tolerance of ±30 ppm/K, while an "N1500" with the code "P3K" will have −1500 ppm/K drift, with a maximum tolerance of ±250 ppm/°C. Note that the IEC and EIA capacitor codes are industry capacitor codes and not the same as military capacitor codes.

Class 1 capacitors include capacitors with different temperature coefficients α. Especially, NP0/CG/C0G capacitors with an α ±0•10⁻⁶ /K and an α tolerance of 30 ppm are technically of great interest. These capacitors have a capacitance variation dC/C of ±0.54% within the temperature range −55 to +125 °C. This enables accurate frequency response over a wide temperature range (in, for example, resonant circuits). The other materials with their special temperature behavior are used to compensate a counter temperature run of parallel connected components like coils in oscillator circuits. Class 1 capacitors exhibit very small tolerances of the rated capacitance.

• Idealized curves of different class 1 ceramic capacitors and representation of the tolerance range of temperature coefficient α
• 
  Idealized curves of different class 1 ceramic capacitors
• 
  representation of the tolerance range of temperature coefficient α

Class 2 ceramic capacitors with their typical tolerances of the temperature dependent capacitance (colored areas)

Class 2 ceramic capacitors have a dielectric with a high permittivity and therefore a better volumetric efficiency than class 1 capacitors, but lower accuracy and stability. The ceramic dielectric is characterized by a nonlinear change of capacitance over the temperature range. The capacitance value also depends on the applied voltage. They are suitable for bypass, coupling and decoupling applications or for frequency discriminating circuits where low losses and high stability of capacitance are less important. They typically exhibit microphony.

Class 2 capacitors are made of ferroelectric materials such as barium titanate (BaTiO
₃) and suitable additives such as aluminium silicate, magnesium silicate and aluminium oxide. These ceramics have high to very high permittivity (200 to 14,000), which depends on the field strength. Hence the capacitance value of class 2 capacitors is nonlinear. It depends on temperature and voltage applied. Additionally class 2 capacitors age over time.[9]

However, the high permittivity supports high capacitance values in small devices. Class 2 capacitors are significantly smaller than class 1 devices at the equal rated capacitance and voltage. They are suitable for applications that require the capacitor to maintain only a minimum value of capacitance, for example, buffering and filtering in power supplies and coupling and decoupling of electric signals.

Class 2 capacitors are labeled according to the change in capacitance over the temperature range. The most widely used classification is based on the EIA RS-198 standard and uses a three-digit code. The first character is a letter that gives the low-end operating temperature. The second gives the high-end operating temperature, and the final character gives capacitance change over that temperature range:

For instance, a Z5U capacitor will operate from +10 °C to +85 °C with a capacitance change of at most +22% to −56%. An X7R capacitor will operate from −55 °C to +125 °C with a capacitance change of at most ±15%.

Some commonly used class 2 ceramic capacitor materials are listed below:

• X8R (−55/+150, ΔC/C₀ = ±15%),
• X7R (−55/+125 °C, ΔC/C₀ = ±15%),
• X6R (−55/+105 °C, ΔC/C₀ = ±15%),
• X5R (−55/+85 °C, ΔC/C₀ = ±15%),
• X7S (−55/+125, ΔC/C₀ = ±22%),
• Z5U (+10/+85 °C, ΔC/C₀ = +22/−56%),
• Y5V (−30/+85 °C, ΔC/C₀ = +22/−82%),

The IEC/EN 60384 -9/22 standard uses another two-digit-code.

In most cases it is possible to translate the EIA code into the IEC/EN code. Slight translation errors occur, but normally are tolerable.

• X7R correlates with 2X1
• Z5U correlates with 2E6
• Y5V similar to 2F4, aberration: ΔC/C₀ = +30/−80% instead of +30/−82%
• X7S similar to 2C1, aberration: ΔC/C₀ = ±20% instead of ±22%
• X8R no IEC/EN code available

Because class 2 ceramic capacitors have lower capacitance accuracy and stability, they require higher tolerance.

For military types the class 2 dielectrics specify temperature characteristic (TC) but not temperature-voltage characteristic (TVC). Similar to X7R, military type BX cannot vary more than 15% over temperature, and in addition, must remain within +15%/-25 % at maximum rated voltage. Type BR has a TVC limit of +15%/-40%.

Class 3 barrier layer or semiconductive ceramic capacitors have very high permittivity, up to 50,000 and therefore a better volumetric efficiency than class 2 capacitors. However, these capacitors have worse electrical characteristics, including lower accuracy and stability. The dielectric is characterized by very high nonlinear change of capacitance over the temperature range. The capacitance value additionally depends on the voltage applied. As well, they have very high losses and age over time.

Barrier layer ceramic capacitors are made of doped ferroelectric materials such as barium titanate (BaTiO
₃). As this ceramic technology improved in the mid-1980s, barrier layer capacitors became available in values of up to 100 µF, and at that time it seemed that they could substitute for smaller electrolytic capacitors.

Design and functional principle of a barrier layer capacitor

Because it is not possible to build multilayer capacitors with this material, only leaded single layer types are offered in the market. [12] [13]

As of 2013 Barrier layer capacitors are considered obsolete, as modern class 2 multilayer ceramics can offer higher capacitances and better performance in a more compact package. As a consequence, these capacitors are no longer standardized by IEC.

• Multi-layer ceramic chip capacitors
• 
  Detailed construction of a multilayer ceramic chip capacitor (MLCC).

  1. Ceramic dielectric
  2. Ceramic or lacquered coating
  3. Metallized electrode
  4. Connecting terminals
• 
  Samples of multilayer ceramic chip capacitors

An MLCC consists of a number of individual capacitors stacked together in parallel and contacted via the terminal surfaces. The starting material for all MLCC chips is a mixture of finely ground granules of paraelectric or ferroelectric raw materials, modified by accurately determined additives.[14] These powdered materials are mixed homogeneously. The composition of the mixture and the size of the powder particles, as small as 10 nm, reflect the manufacturer's expertise.

A thin ceramic foil is cast from a suspension of the powder with a suitable binder. This foil is rolled up for transport. Unrolled again, it is cut into equal-sized sheets, which are screen printed with a metal paste. These sheets become the electrodes. In an automated process, these sheets are stacked in the required number of layers and solidified by pressure. Besides the relative permittivity, the size and number of layers determines the later capacitance value. The electrodes are stacked in an alternating arrangement slightly offset from the adjoining layers so that they each can later be connected on the offset side, one left, one right. The layered stack is pressed and then cut into individual components. High mechanical precision is required, for example, to produce a 500 or more layer stack of size "0201" (0.5 mm × 0.3 mm).

After cutting, the binder is burnt out of the stack. This is followed by sintering at temperatures between 1,200 and 1,450 °C producing the final, mainly crystalline, structure. This burning process creates the desired dielectric properties. Burning is followed by cleaning and then metallization of both end surfaces. Through the metallization, the ends and the inner electrodes are connected in parallel and the capacitor gets its terminals. Finally a 100% measuring of the electrical values will be done and the taping for automated processing in a manufacturing device are performed.

Simplified representation of the manufacturing process for the production of multilayer ceramic chip capacitors

The capacitance formula (C) of a MLCC capacitor is based on the formula for a plate capacitor enhanced with the number of layers:
${\displaystyle C=\varepsilon \cdot {{n\cdot A} \over {d}}}$
where ε stands for dielectric permittivity; A for electrode surface area; n for the number of layers; and d for the distance between the electrodes.

Miniaturizing of MLCC chip capacitors during 1995 to 2005

A thinner dielectric or a larger electrode area each increase the capacitance value, as will a dielectric material of higher permittivity.

With the progressive miniaturization of digital electronics in recent decades, the components on the periphery of the integrated logic circuits have been scaled down as well. Shrinking an MLCC involves reducing the dielectric thickness and increasing the number of layers. Both options require huge efforts and are connected with a lot of expertise.

In 1995 the minimum thickness of the dielectric was 4 µm. By 2005 some manufacturers produced MLCC chips with layer thicknesses of 1 µm. As of 2010, the minimum thickness is about 0.5 µm.[1] The field strength in the dielectric increased to 35 V/µm.[15]

The size reduction of these capacitors is achieved reducing powder grain size, the assumption to make the ceramic layers thinner. In addition, the manufacturing process became more precisely controlled, so that more and more layers can be stacked.

Between 1995 and 2005, the capacitance of a Y5V MLCC capacitor of size 1206 was increased from 4.7 μF to 100 μF.[16] Meanwhile, (2013) a lot of producers can deliver class 2 MLCC capacitors with a capacitance value of 100 μF in the chip-size 0805.[17]

MLCCs don't have leads, and as a result they are usually smaller than their counterparts with leads. They don't require through-hole access in a PCB to mount and are designed to be handled by machines rather than by humans. As a result, surface-mount components like MLCCs are typically cheaper.

MLCCs are manufactured in standardized shapes and sizes for comparable handling. Because the early standardization was dominated by American EIA standards the dimensions of the MLCC chips were standardized by EIA in units of inches. A rectangular chip with the dimensions of 0.06 inch length and 0.03 inch width is coded as "0603". This code is international and in common use. JEDEC (IEC/EN), devised a second, metric code. The EIA code and the metric equivalent of the common sizes of multilayer ceramic chip capacitors, and the dimensions in mm are shown in the following table. Missing from the table is the measure of the height "H". This is generally not listed, because the height of MLCC chips depends on the number of layers and thus on the capacitance. Normally, however, the height H does not exceed the width W.

Table of the dimension codes and the corresponding dimensions of MLCC chip capacitors

Drawing	EIA inch code	Dimensions L × W inch × inch	IEC/EN metric code	Dimensions L × W mm × mm		EIA inch code	Dimensions LxW inch × inch	IEC/EN metric code	Dimensions L × W mm × mm
Dimensions L×W×H of the multi-layer ceramic chip capacitors	01005	0.016 × 0.0079	0402	0.4 × 0.2		1806	0.18 × 0.063	4516	4.5 × 1.6
	015015	0.016 × 0.016	0404	0.4 × 0.4		1808	0.18 × 0.079	4520	4.5 × 2.0
	0201	0.024 × 0.012	0603	0.6 × 0.3		1812	0.18 × 0.13	4532	4.5 × 3.2
	0202	0.02 × 0.02	0505	0.5 × 0.5		1825	0.18 × 0.25	4564	4.5 × 6.4
	0302	0.03 × 0.02	0805	0.8 × 0.5		2010	0.20 × 0.098	5025	5.0 × 2.5
	0303	0.03 × 0.03	0808	0.8 × 0.8		2020	0.20 × 0.20	5050	5.08 × 5.08
	0504	0.05 × 0.04	1310	1.3 × 1.0		2220	0.225 × 0.197	5750	5.7 × 5.0
	0402	0.039 × 0.020	1005	1.0 × 0.5		2225	0.225 × 0.25	5664/5764	5.7 × 6.4
	0603	0.063 × 0.031	1608	1.6 × 0.8		2512	0.25 × 0.13	6432	6.4 × 3.2
	0805	0.079 × 0.049	2012	2.0 × 1.25		2520	0.25 × 0.197	6450	6.4 × 5.0
	1008	0.098 × 0.079	2520	2.5 × 2.0		2920	0.29 × 0.197	7450	7.4 × 5.0
	1111	0.11 × 0.11	2828	2.8 × 2.8		3333	0.33 × 0.33	8484	8.38 × 8.38
	1206	0.126 × 0.063	3216	3.2 × 1.6		3640	0.36 × 0.40	9210	9.2 × 10.16
	1210	0.126 × 0.10	3225	3.2 × 2.5		4040	0.4 × 0.4	100100	10.2 × 10.2
	1410	0.14 × 0.10	3625	3.6 × 2.5		5550	0.55 × 0.5	140127	14.0 × 12.7
	1515	0.15 × 0.15	3838	3.81 × 3.81		8060	0.8 × 0.6	203153	20.3 × 15.3

• Influence of the metallization on the voltage dependence of X7R ceramic multilayer chip capacitors
• 
  Structure of the electrodes and the NME respectively BME metallization of the terminals of MLCC cchips
• 
  Influence of the NME respectively BME metallization for class 2 X7R MLCC chips on the voltage dependence of capacitance.

A particular problem in the production of multilayer ceramic chip capacitors at the end of the 1990s was a strong price increase of the metals used for the electrodes and terminals. The original choices were the non-oxidizable noble metals silver and palladium which can withstand high sintering temperatures of 1200 to 1400 °C. They were called "NME" (Noble Metal Electrode) and offered very good electrical properties to class 2 capacitors. The price increase of these metals greatly increased capacitor prices.

Cost pressures led to the development of BME (Base Metal Electrodes) using the much cheaper materials nickel and copper.[18]

But BME metallization produced different electrical properties; for example, the voltage dependence of X7R capacitors increased significantly (see picture). Even the loss factor and the impedance behavior of class 2 ceramic capacitors were lessened by BME metallization.

For class 2 ceramic capacitors, because of their use in applications where it is usually not very important for the stability of the electrical properties, these negative changes, for cost reasons, were finally accepted by the market, while the NME metallization was maintained in the class 1 ceramic capacitors.

Maximal available capacitance values of MLCC Chips in case size 2012. (Status April 2017)

Capacitance of MLCC chips depends on the dielectric, the size and the required voltage (rated voltage). Capacitance values start at about 1pF. The maximum capacitance value is determined by the production technique. For X7R that is 47 µF, for Y5V: 100 µF.

The picture right shows the maximum capacitance for class 1 and class 2 multilayer ceramic chip capacitors. The following two tables, for ceramics NP0/C0G and X7R each, list for each common case size the maximum available capacitance value and rated voltage of the leading manufacturers Murata, TDK, KEMET, AVX. (Status April 2017)

• Comparison of different MLCC designs
• 
  Standard MLCC chip design
• 
  Low-ESL design of an MLCC chip
• 
  MLCC chip array

In the region of its resonance frequency, a capacitor has the best decoupling properties for noise or electromagnetic interference. The resonance frequency of a capacitor is determined by the inductance of the component. The inductive parts of a capacitor are summarized in the equivalent series inductance, or ESL. (Note that L is the electrical symbol for inductance.) The smaller the inductance, the higher the resonance frequency.

Because, especially in digital signal processing, switching frequencies have continued to rise, the demand for high frequency decoupling or filter capacitors increases. With a simple design change the ESL of an MLCC chip can be reduced. Therefore, the stacked electrodes are connected on the longitudinal side with the connecting terminations. This reduces the distance that the charge carriers flow over the electrodes, which reduces inductance of the component.[19]

For example, the result for X7R with 0.1 µF in the size of 0805, with a resonance frequency of about 16 MHz increases to about 22 MHz if the chip has an 0508-size with terminations at the longitudinal side.

Another possibility is to form the device as an array of capacitors. Here, several individual capacitors are built in a common housing. Connecting them in parallel, the resulting ESL as well as ESR values of the components are reduced.

• X2Y decoupling capacitor
• 
  X2Y decoupling capacitors with different case sizes
• 
  Inner construction of a X2Y capacitor
• 
  Circuit diagram of a X2Y capacitor in a decoupling circuit

A standard multi-layer ceramic capacitor has many opposing electrode layers stacked inside connected with two outer terminations. The X2Y ceramic chip capacitor however is a 4 terminal chip device. It is constructed like a standard two-terminal MLCC out of the stacked ceramic layers with an additional third set of shield electrodes incorporated in the chip. These shield electrodes surround each existing electrode within the stack of the capacitor plates and are low ohmic contacted with two additional side terminations across to the capacitor terminations. The X2Y construction results in a three-node capacitive circuit that provides simultaneous line-to-line and line-to-ground filtering.[20][21][22]

Capable of replacing 2 or more conventional devices, the X2Y ceramic capacitors are ideal for high frequency filtering or noise suppression of supply voltages in digital circuits, and can prove invaluable in meeting stringent EMC demands in dc motors, in automotive, audio, sensor and other applications.[23][24]

The X2Y footprint results in lower mounted inductance.[25] This is particularly of interest for use in high-speed digital circuits with clock rates of several 100 MHz and upwards. There the decoupling of the individual supply voltages on the circuit board is difficult to realize due to parasitic inductances of the supply lines. A standard solution with conventional ceramic capacitors requires the parallel use of many conventional MLCC chips with different capacitance values. Here X2Y capacitors are able to replace up to five equal-sized ceramic capacitors on the PCB.[26] However, this particular type of ceramic capacitor is patented, so these components are still comparatively expensive.

An alternative to X2Y capacitors may be a three-terminal capacitor.[27]

Ceramic is on the one hand a very solid material; on the other hand, it breaks even at relatively low mechanical stress.[28] MLCC chips as surface-mounted components are susceptible to flexing stresses since they are mounted directly on the substrate. They are stuck between soldered joints on the printed circuit board (PCB), and are often exposed to mechanical stresses, for example, if vibration or a bump impacts the circuit board. They are also more sensitive to thermal stresses than leaded components. Excess solder fillet height can multiply these stresses and cause chip cracking. Of all influencing factors, causing a mechanical shock stress to the PCB proved to be the most critical one.[29] The reason is that forces induced by those kinds of stresses are more or less transmitted undampened to the components via the PCB and solder joints.

• MLCC chips – correct mounted – cracked chip – substrate bending test
• 
  Correct mounted and soldered MLCC chip on a PCB
• 
  Micrograph of broken ceramic in a MLCC chip
• 
  Simplified figure of a bending test for soldered MLCC

The capability of MLCC chips to withstand mechanical stress is tested by a so-called substrate bending test. Here, a test PCB with a soldered MLCC chip between two support points is bent by a punch at a path length of 1 to 3mm. The path length depends on the requirements that come out from the application. If no crack appears, the capacitors are able to withstand the wanted requirements. Cracks are usually detected by a short circuit or a change of the capacitance value in the deflected state.

The bending strength of the MLCC chip differs by the property of the ceramic, the size of the chip and the design of the capacitors. Without any special design features, NP0/C0G class 1 ceramic MLCC chips reach a typical bending strength of 2mm while larger types of X7R, Y5V class 2 ceramic chips achieved only a bending strength of approximately 1mm. Smaller chips, such as the size of 0402, reached in all types of ceramics larger bending strength values.

With special design features, particularly by special design of the electrodes and the terminations, the bending strength can be improved. For example, an internal short circuit arises by the contact of two electrodes with opposite polarity, which will be produced at the break of the ceramic in the region of the terminations. This can be prevented when the overlap surfaces of the electrodes are reduced. This is achieved e.g. by an "Open Mode Design" (OMD). Here a break in the region of the terminations only reduce the capacitance value a little bit (AVX, KEMET).

• Different MLCC constructions to minimize mechanical stress
• 
  Standard MLCC chip, short circuit possible if ceramic breaks due to mechanical stress
• 
  „Open-Mode-Design" MLCC chip, a break only reduces the capacitance value
• 
  "Floating-Electrode-Design"-MLCC, a break only reduces the capacitance value
• 
  "Flex-Termination" - MLCC chips, a flexible contact layer prevents breaking of the ceramic.[30]

With a similar construction called "Floating Electrode Design" (FED) or "Multi-layer Serial Capacitors" (MLSC), also, only capacitance reduction results if parts of the capacitor body break. This construction works with floating electrodes without any conductive connection to the termination. A break doesn't lead to a short, only to capacitance reduction. However, both structures lead to larger designs with respect to a standard MLCC version with the same capacitance value.

The same volume with respect to standard MLCCs is achieved by the introduction of a flexible intermediate layer of a conductive polymer between the electrodes and the termination called "Flexible Terminations" (FT-Cap) or "Soft Terminations". In this construction, the rigid metallic soldering connection can move against the flexible polymer layer, and thus can absorb the bending forces, without resulting in a break in the ceramic.[31]

Suppression capacitors are effective interference reduction components because their electrical impedance decreases with increasing frequency, so that at higher frequencies they short circuit electrical noise and transients between the lines, or to ground. They therefore prevent equipment and machinery (including motors, inverters, and electronic ballasts, as well as solid-state relay snubbers and spark quenchers) from sending and receiving electromagnetic and radio frequency interference as well as transients in across-the-line (X capacitors) and line-to-ground (Y capacitors) connections. X capacitors effectively absorb symmetrical, balanced, or differential interference. Y capacitors are connected in a line bypass between a line phase and a point of zero potential, to absorb asymmetrical, unbalanced, or common-mode interference.[32][33][34]

• RFI/EMI suppression with X- and Y-capacitors for equipment without and with additional safety insulation
• 
  Appliance Class I capacitor connection
• 
  Appliance Class II capacitor connection

EMI/RFI suppression capacitors are designed so that any remaining interference or electrical noise does not exceed the limits of EMC directive EN 50081.[35] Suppression components are connected directly to mains voltage for 10 to 20 years or more and are therefore exposed to potentially damaging overvoltages and transients. For this reason, suppression capacitors must comply with the safety and non-flammability requirements of international safety standards such as

• Europe: EN 60384-14,
• USA: UL 1414, UL 1283
• Canada: CSA C22.2, No.1, CSA C22.2, No.8
• China: CQC (GB/T 14472-1998)

RFI capacitors that fulfill all specified requirements are imprinted with the certification mark of various national safety standards agencies. For power line applications, special requirements are placed on the non-flammability of the coating and the epoxy resin impregnating or coating the capacitor body. To receive safety approvals, X and Y powerline-rated capacitors are destructively tested to the point of failure. Even when exposed to large overvoltage surges, these safety-rated capacitors must fail in a fail-safe manner that does not endanger personnel or property.

As of 2012 most ceramic capacitors used for EMI/RFI suppression were leaded ones for through-hole mounting on a PCB,[36][37] the surface-mount technique is becoming more and more important. For this reason, in recent years a lot of MLCC chips for EMI/RFI suppression from different manufacturers have received approvals and fulfill all requirements given in the applicable standards.[36][38][39][40][41]

• Different styles of ceramic capacitors for power electronic
• 
  Doorknob style high voltage ceramic capacitor
• 
  Disc style power ceramic capacitor
• 
  Tubular or pot style power ceramic capacitor

Although the materials used for large power ceramic capacitors mostly are very similar to those used for smaller ones, ceramic capacitors with high to very high power or voltage ratings for applications in power systems, transmitters and electrical installations are often classified separately, for historical reasons. The standardization of ceramic capacitors for lower power is oriented toward electrical and mechanical parameters as components for use in electronic equipment. The standardization of power capacitors, contrary to that, is strongly focused on protecting personnel and equipment, given by the local regulating authority.

Power ceramic capacitors in a radio-frequency transmitter station

As modern electronic equipment gained the ability to handle power levels that were previously the exclusive domain of "electrical power" components, the distinction between the "electronic" and "electrical" power ratings has become less distinct. In the past, the boundary between these two families was approximately at a reactive power of 200 volt-amps, but modern power electronics can handle increasing amounts of power.

Power ceramic capacitors are mostly specified for much higher than 200 volt-amps. The great plasticity of ceramic raw material and the high dielectric strength of ceramics deliver solutions for many applications and are the reasons for the enormous diversity of styles within the family of power ceramic capacitors. These power capacitors have been on the market for decades. They are produced according to the requirements as class 1 power ceramic capacitors with high stability and low losses or class 2 power ceramic capacitors with high volumetric efficiency.

Class 1 power ceramic capacitors are used for resonant circuit application in transmitter stations. Class 2 power ceramic capacitors are used for circuit breakers, for power distribution lines, for high voltage power supplies in laser-applications, for induction furnaces and in voltage-doubling circuits. Power ceramic capacitors can be supplied with high rated voltages in the range of 2 kV up to 100 kV.[42]

The dimensions of these power ceramic capacitors can be very large. At high power applications the losses of these capacitors can generate a lot of heat. For this reason some special styles of power ceramic capacitors have pipes for water-cooling.

Series-equivalent circuit model of a ceramic capacitor

All electrical characteristics of ceramic capacitors can be defined and specified by a series equivalent circuit composed out of an idealized capacitance and additional electrical components, which model all losses and inductive parameters of a capacitor. In this series-equivalent circuit the electrical characteristics of a capacitors is defined by

• C, the capacitance of the capacitor,
• R_insul, the insulation resistance of the dielectric, not to be confused with the insulation of the housing
• R_ESR, the equivalent series resistance, which summarizes all ohmic losses of the capacitor, usually abbreviated as "ESR".
• L_ESL, the equivalent series inductance, which is the effective self-inductance of the capacitor, usually abbreviated as "ESL".

The use of a series equivalent circuit instead of a parallel equivalent circuit is defined in IEC/EN 60384-1.

The "rated capacitance" C_R or "nominal capacitance" C_N is the value for which the capacitor has been designed. The actual capacitance depends on the measuring frequency and the ambient temperature. Standardized conditions for capacitors are a low-voltage AC measuring method at a temperature of 20 °C with frequencies of

• Class 1 ceramic capacitors
  • C_R ≤ 100 pF at 1 MHz, measuring voltage 5 V
  • C_R > 100 pF at 1 kHz, measuring voltage 5 V
• Class 2 ceramic capacitors
  • C_R ≤ 100 pF at 1 MHz, measuring voltage 1 V
  • 100 pF < C_R ≤ 10 µF at 1 kHz, measuring voltage 1 V
  • C_R > 10 µF at 100/120 Hz, measuring voltage 0.5 V

Capacitors are available in different, geometrically increasing preferred values as specified in the E series standards specified in IEC/EN 60063. According to the number of values per decade, these were called the E3, E6, E12, E24, etc. series. The units used to specify capacitor values includes everything from picofarad (pF), nanofarad (nF), microfarad (µF) and farad (F).

The percentage of allowed deviation of the capacitance from the rated value is called capacitance tolerance. The actual capacitance value must be within the tolerance limits, or the capacitor is out of specification. For abbreviated marking in tight spaces, a letter code for each tolerance is specified in IEC/EN 60062.

The required capacitance tolerance is determined by the particular application. The narrow tolerances of E24 to E96 will be used for high-quality class 1 capacitors in circuits such as precision oscillators and timers. On the other hand, for general applications such as non-critical filtering or coupling circuits, for class 2 capacitors the tolerance series E12 down to E3 are sufficient.

Capacitance of ceramic capacitors varies with temperature. The different dielectrics of the many capacitor types show great differences in temperature dependence. The temperature coefficient is expressed in parts per million (ppm) per degree Celsius for class 1 ceramic capacitors or in percent (%) over the total temperature range for class 2 capacitors.

Frequency dependence of capacitance for ceramic X7R and Y5V class 2 capacitors (curve of NP0 class 1 for comparisation)

Most discrete capacitor types have greater or smaller capacitance changes with increasing frequencies. The dielectric strength of class 2 ceramic and plastic film diminishes with rising frequency. Therefore, their capacitance value decreases with increasing frequency. This phenomenon is related to the dielectric relaxation in which the time constant of the electrical dipoles is the reason for the frequency dependence of permittivity. The graph on the right hand side shows typical frequency behavior for class 2 vs class 1 capacitors.

DC Bias characteristic of ferroelectrics ceramic materials

Capacitance of ceramic capacitors may also change with applied voltage. This effect is more prevalent in class 2 ceramic capacitors. The ferroelectric material depends on the applied voltage.[43][44] The higher the applied voltage, the lower the permittivity. Capacitance measured or applied with higher voltage can drop to values of -80% of the value measured with the standardized measuring voltage of 0.5 or 1.0 V. This behavior is a small source of nonlinearity in low-distortion filters and other analog applications. In audio applications this can be the reason for harmonic distortions.

• Voltage dependence of capacitance for some different class 2 ceramic capacitors
• 
  Simplified diagram of the change in capacitance as a function of the applied voltage for 25-V capacitors in different kind of ceramic grades
• 
  Simplified diagram of the change in capacitance as a function of applied voltage for X7R ceramics with different rated voltages

The voltage dependence of capacitance in the both diagrams above shows curves from ceramic capacitors with NME metallization. For capacitors with BME metallization the voltage dependence of capacitance increased significantly.[45][46][47][48]

For most capacitors, a physically conditioned dielectric strength or a breakdown voltage usually could be specified for each dielectric material and thickness. This is not possible with ceramic capacitors. The breakdown voltage of a ceramic dielectric layer may vary depending on the electrode material and the sintering conditions of the ceramic up to a factor of 10. A high degree of precision and control of process parameters is necessary to keep the scattering of electrical properties for today's very thin ceramic layers within specified limits.

The voltage proof of ceramic capacitors is specified as rated voltage (UR). This is the maximum DC voltage that may be continuously applied to the capacitor up to the upper temperature limit. This guaranteed voltage proof is tested according to the voltages shown in the adjacent table.

Furthermore, in periodic life time tests (endurance tests) the voltage proof of ceramic capacitors is tested with increased test voltage (120 to 150% of U_R) to ensure safe construction.

Simplified series-equivalent circuit of a capacitor for higher frequencies (above); vector diagram with electrical reactances X_ESL and X_C and resistance ESR and for illustration the impedance Z and dissipation factor tan δ

The frequency dependent AC resistance of a capacitor is called impedance ${\displaystyle Z}$ and is a complex ratio of voltage to current in an AC circuit. Impedance extends the concept of Ohm's law to AC circuits, and possesses both magnitude and phase at a particular frequency, unlike resistance, which has only magnitude.

Impedance is a measure of the ability of the capacitor to pass alternating currents. In this sense impedance can be used like Ohms law

${\displaystyle Z={\frac {\hat {u}}{\hat {\imath }}}={\frac {U_{\mathrm {AC} }}{I_{\mathrm {AC} }}}.}$

to calculate either the peak or the effective value of the current or the voltage.

As shown in the series-equivalent circuit of a capacitor, the real-world component includes an ideal capacitor ${\displaystyle C}$, an inductance ${\displaystyle L}$ and a resistor ${\displaystyle R}$.

To calculate the impedance ${\displaystyle Z}$ the resistance and the both reactances have to be added geometrically

${\displaystyle Z={\sqrt {{ESR}^{2}+(X_{\mathrm {C} }+(-X_{\mathrm {L} }))^{2}}}}$

wherein the capacitive reactance (Capacitance) is

${\displaystyle X_{C}=-{\frac {1}{\omega C}}}$

and an inductive reactance (Inductance) is

${\displaystyle X_{L}=\omega L_{\mathrm {ESL} }}$.

In the special case of resonance, in which both reactive resistances have the same value (${\displaystyle X_{C}=X_{L}}$), then the impedance will only be determined by ${\displaystyle {ESR}}$.

Typical curves of the impedance of X7R and NP0-MLCC-Chips

Data sheets of ceramic capacitors only specify the impedance magnitude ${\displaystyle Z}$. The typical impedance curve shows that with increasing frequency, impedance decreases, down to a minimum. The lower the impedance, the more easily alternating currents can pass through the capacitor. At the minimum point of the curve, the point of resonance, where X_C has the same value as X_L, the capacitor exhibits its lowest impedance value. Here only the ohmic ESR determines the impedance. With frequencies above the resonance, impedance increases again due to the ESL.

The summarized losses in ceramic capacitors are ohmic AC losses. DC losses are specified as "leakage current" or "insulating resistance" and are negligible for an AC specification. These AC losses are nonlinear and may depend on frequency, temperature, age, and for some special types, on humidity. The losses result from two physical conditions,

• line losses with internal supply line resistances, the contact resistance of the electrode contact, the line resistance of the electrodes
• the dielectric losses out of the dielectric polarization

The largest share of these losses in larger capacitors is usually the frequency dependent ohmic dielectric losses. Regarding the IEC 60384-1 standard, the ohmic losses of capacitors are measured at the same frequency used to measure capacitance. These are:

• 100 kHz, 1 MHz (preferred) or 10 MHz for ceramic capacitors with C_R ≤ 1 nF:
• 1 kHz or 10 kHz for ceramic capacitors with 1 nF < C_R ≤ 10 μF
• 50/60 Hz or 100/120 Hz for ceramic capacitors with C_R > 10 μF

Results of the summarized resistive losses of a capacitor may be specified either as equivalent series resistance (ESR), as dissipation factor (DF, tan δ), or as quality factor (Q), depending on the application requirements.

Class 2 capacitors are mostly specified with the dissipation factor, tan δ. The dissipation factor is determined as the tangent of the reactance ${\displaystyle X_{C}}$ - ${\displaystyle X_{L}}$ and the ESR, and can be shown as the angle δ between the imaginary and impedance axes in the above vector diagram, see paragraph "Impedance".

If the inductance ${\displaystyle ESL}$ is small, the dissipation factor can be approximated as:

${\displaystyle \tan \delta =ESR\cdot \omega C}$

Class 1 capacitors with very low losses are specified with a dissipation factor and often with a quality factor (Q). The quality factor is defined as the reciprocal of the dissipation factor.

${\displaystyle Q={\frac {1}{tan\delta }}={\frac {f_{0}}{B}}\ }$

The Q factor represents the effect of electrical resistance, and characterizes a resonator's bandwidth ${\displaystyle B}$ relative to its center or resonant frequency ${\displaystyle f_{0}}$. A high Q value is a mark of the quality of the resonance for resonant circuits.

In accordance with IEC 60384-8/-21/-9/-22 ceramic capacitors may not exceed the following dissipation factors:

The ohmic losses of ceramic capacitors are frequency, temperature and voltage dependent. Additionally, class 2 capacitor measurements change because of aging. Different ceramic materials have differing losses over the temperature range and the operating frequency. The changes in class 1 capacitors are in the single-digit range while class 2 capacitors have much higher changes.

Electrical resonance occurs in a ceramic capacitor at a particular resonance frequency where the imaginary parts of the capacitor impedance and admittances cancel each other. This frequency where X_C is as high as X_L is called the self-resonant frequency and can be calculated with:

${\displaystyle \omega ={\frac {1}{\sqrt {LC}}}}$

where ω = 2πf, in which f is the resonance frequency in Hertz, L is the inductance in henries, and C is the capacitance in farads.

The smaller the capacitance C and the inductance L the higher is the resonance frequency. The self-resonant frequency is the lowest frequency at which impedance passes through a minimum. For any AC application the self-resonant frequency is the highest frequency at which a capacitor can be used as a capacitive component. At frequencies above the resonance, the impedance increases again due to ESL: the capacitor becomes an inductor with inductance equal to capacitor's ESL, and resistance equal to ESR at the given frequency.

ESL in industrial capacitors is mainly caused by the leads and internal connections used to connect the plates to the outside world. Larger capacitors tend to higher ESL than small ones, because the distances to the plate are longer and every millimeter increases inductance.

Ceramic capacitors, which are available in the range of very small capacitance values (pF and higher) are already out of their smaller capacitance values suitable for higher frequencies up to several 100 MHz (see formula above). Due to the absence of leads and proximity to the electrodes, MLCC chips have significantly lower parasitic inductance than f. e. leaded types, which makes them suitable for higher frequency applications. A further reduction of parasitic inductance is achieved by contacting the electrodes on the longitudinal side of the chip instead of the lateral side.

Sample self-resonant frequencies for one set of NP0/C0G and one set of X7R ceramic capacitors are:[49]

Note that X7Rs have better frequency response than C0Gs. It makes sense, however, since class 2 capacitors are much smaller than class 1, so they ought to have lower parasitic inductance.

Aging of different Class 2 ceramic capacitors compared with NP0-Class 1 ceramic capacitor

In ferroelectric class 2 ceramic capacitors capacitance decreases over time. This behavior is called "aging". Aging occurs in ferroelectric dielectrics, where domains of polarization in the dielectric contribute to total polarization. Degradation of the polarized domains in the dielectric decreases permittivity over time so that the capacitance of class 2 ceramic capacitors decreases as the component ages.[50] [51]

The aging follows a logarithmic law. This law defines the decrease of capacitance as a percentage for a time decade after the soldering recovery time at a defined temperature, for example, in the period from 1 to 10 hours at 20 °C. As the law is logarithmic, the percentage loss of capacitance will twice between 1 h and 100 h and 3 times between 1 h and 1000 h and so on. So aging is fastest near the beginning, and the capacitance value effectively stabilizes over time.

The rate of aging of class 2 capacitors mainly depends on the materials used. A rule of thumb is, the higher the temperature dependence of the ceramic, the higher the aging percentage. The typical aging of X7R ceramic capacitors is about 2.5% per decade[52] The aging rate of Z5U ceramic capacitors is significantly higher and can be up to 7% per decade.

The aging process of class 2 capacitors may be reversed by heating the component above the Curie point.[2]

Class 1 capacitors do not experience ferroelectric aging like Class 2's. But environmental influences such as higher temperature, high humidity and mechanical stress can, over a longer period of time, lead to a small irreversible decline in capacitance, sometimes also called aging. The change of capacitance for P 100 and N 470 Class 1's is lower than 1%, for capacitors with N 750 to N 1500 ceramics it is ≤ 2%.

The resistance of the dielectric is never infinite, leading to some level of DC "leakage current", which contributes to self-discharge. For ceramic capacitors this resistance, placed in parallel with the capacitor in the series-equivalent circuit of capacitors, is called "insulation resistance R_ins". The insulation resistance must not be confused with the outer isolation with respect to the environment.

The rate of self-discharge with decreasing capacitor voltage follows the formula

${\displaystyle u(t)=U_{0}\cdot \mathrm {e} ^{-t/\tau _{\mathrm {s} }},}$

With the stored DC voltage ${\displaystyle U_{0}}$ and the self-discharge constant

${\displaystyle \tau _{\mathrm {s} }=R_{\mathrm {ins} }\cdot C}$

That means, after ${\displaystyle \tau _{\mathrm {s} }\,}$ capacitor voltage ${\displaystyle U_{0}}$ dropped to 37% of the initial value.

The insulation resistance given in the unit MΩ (10⁶ Ohm) as well as the self-discharge constant in seconds is an important parameter for the quality of the dielectric insulation. These time values are important, for example, when a capacitor is used as timing component for relays or for storing a voltage value as in a sample and hold circuits or operational amplifiers.

In accordance with the applicable standards, Class 1 ceramic capacitors have an R_ins ≥ 10,000 MΩ for capacitors with C_R ≤ 10 nF or τ_s ≥ 100 s for capacitors with C_R > 10 nF. Class 2 ceramic capacitors have an R_ins ≥ 4,000 MΩ for capacitors with C_R ≤ 25 nF or τ_s ≥ 100 s for capacitors with C_R > 25 nF.

Insulation resistance and thus the self-discharge time rate are temperature dependent and decrease with increasing temperature at about 1 MΩ per 60 °C.

Dielectric absorption is the name given to the effect by which a capacitor, which has been charged for a long time, discharges only incompletely. Although an ideal capacitor remains at zero volts after discharge, real capacitors will develop a small voltage coming from time-delayed dipole discharging, a phenomenon that is also called dielectric relaxation, "soakage" or "battery action".

In many applications of capacitors dielectric absorption is not a problem but in some applications, such as long-time-constant integrators, sample-and-hold circuits, switched-capacitor analog-to-digital converters and very low-distortion filters, it is important that the capacitor does not recover a residual charge after full discharge, and capacitors with low absorption are specified. The voltage at the terminals generated by dielectric absorption may in some cases possibly cause problems in the function of an electronic circuit or can be a safety risk to personnel. In order to prevent shocks, most very large capacitors like power capacitors are shipped with shorting wires that are removed before use.[53]

All class 2 ceramic capacitors using ferroelectric ceramics exhibit piezoelectricity, and have a piezoelectric effect called microphonics, microphony or in audio applications squealing.[54] Microphony describes the phenomenon wherein electronic components transform mechanical vibrations into an electrical signal which in many cases is undesired noise.[55] Sensitive electronic preamplifiers generally use class 1 ceramic and film capacitors to avoid this effect.[55]

In the reverse microphonic effect, the varying electric field between the capacitor plates exerts a physical force, moving them as a speaker.[55] High current impulse loads or high ripple currents can generate audible acoustic sound coming from the capacitor, but discharges the capacitor and stresses the dielectric.[56][57][58]

Ceramic capacitors may experience changes to their electrical parameters due to soldering stress. The heat of the solder bath, especially for SMD styles, can cause changes of contact resistance between terminals and electrodes. For ferroelectric class 2 ceramic capacitors, the soldering temperature is above the Curie point. The polarized domains in the dielectric are going back and the aging process of class 2 ceramic capacitors is starting again.[2]

Hence after soldering a recovery time of approximately 24 hours is necessary. After recovery some electrical parameters like capacitance value, ESR, leakage currents are changed irreversibly. The changes are in the lower percentage range depending on the style of capacitor.

The standardization for all electrical, electronic components and related technologies follows the rules given by the International Electrotechnical Commission (IEC),[59] a non-profit, non-governmental international standards organization.[60][61]

The definition of the characteristics and the procedure of the test methods for capacitors for use in electronic equipment are set out in the generic specification:

• IEC 60384-1, Fixed capacitors for use in electronic equipment - Part 1: Generic specification

The tests and requirements to be met by ceramic capacitors for use in electronic equipment for approval as standardized types are set out in the following sectional specifications:

• IEC 60384-8, Fixed capacitors of ceramic dielectric, Class 1
• IEC 60384-9, Fixed capacitors of ceramic dielectric, Class 2
• IEC 60384-21, Fixed surface mount multilayer capacitors of ceramic dielectric, Class 1
• IEC 60384-22, Fixed surface mount multilayer capacitors of ceramic dielectric, Class 2

Multilayer ceramic capacitors are increasingly used to replace tantalum and low capacitance aluminium electrolytic capacitors in applications such as bypass or high frequency switched-mode power supplies as their cost, reliability and size becomes competitive. In many applications, their low ESR allows the use of a lower nominal capacitance value.[62][63][64][65][66]

For features and disadvantages of ceramic capacitors see main article Types of capacitor#Capacitor features comparisons

If space permits ceramic capacitors, like most other electronic components, have imprinted markings to indicate the manufacturer, the type, their electrical and thermal characteristics and their date of manufacture. In the ideal case, if they are large enough, the capacitor will be marked with:

• manufacturer's name or trademark;
• manufacturer's type designation;
• rated capacitance;
• tolerance on rated capacitance
• rated voltage and nature of supply (AC or DC)
• climatic category or rated temperature;
• year and month (or week) of manufacture;
• certification marks of safety standards (for safety EMI/RFI suppression capacitors)

Smaller capacitors use a shorthand notation, to display all the relevant information in the limited space. The most commonly used format is: XYZ J/K/M VOLTS V, where XYZ represents the capacitance (calculated as XY × 10^Z pF), the letters J, K or M indicate the tolerance (±5%, ±10% and ±20% respectively) and VOLTS V represents the working voltage.

• A capacitor with the following text on its body: 105K 330V has a capacitance of 10 × 10⁵ pF = 1 µF (K = ±10%) with a working voltage of 330 V.
• A capacitor with the following text: 473M 100V has a capacitance of 47 × 10³ pF = 47 nF (M = ±20%) with a working voltage of 100 V.

Capacitance, tolerance and date of manufacture can be identified with a short code according to IEC/EN 60062. Examples of short-marking of the rated capacitance (microfarads):

• µ47 = 0.47 µF
• 4µ7 = 4.7 µF
• 47µ = 47 µF

The date of manufacture is often printed in accordance with international standards.

• Version 1: coding with year/week numeral code, "1208" is "2012, week number 8".
• Version 2: coding with year code/month code,

Year code: "R" = 2003, "S"= 2004, "T" = 2005, "U" = 2006, "V" = 2007, "W" = 2008, "X" = 2009, "A" = 2010, "B" = 2011, "C" = 2012, "D" = 2013 etc.

Month code: "1" to "9" = Jan. to Sept., "O" = October, "N" = November, "D" = December

"X5" is then "2009, May"

For very small capacitors like MLCC chips no marking is possible. Here only the traceability of the manufacturers can ensure the identification of a type.

The identification of modern capacitors has no detailed color coding.