Chip-scale package

A chip scale package or chip-scale package (CSP) is a type of integrated circuit package.[1]

Top and bottom of a WL-CSP package sitting on the face of a U.S. penny. In the top-right, a SOT23 package is shown for comparison.

Originally, CSP was the acronym for chip-size packaging. Since only a few packages are chip size, the meaning of the acronym was adapted to chip-scale packaging. According to IPC's standard J-STD-012, Implementation of Flip Chip and Chip Scale Technology, in order to qualify as chip scale, the package must have an area no greater than 1.2 times that of the die and it must be a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.

The concept was first proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable in 1993. The first concept demonstration however came from Mitsubishi Electric.[2]

The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die: such a package is called a wafer-level package (WLP) or a wafer-level chip-scale package (WL-CSP). WL-CSP had been in development since 1990s, and several companies begun volume production in early 2000, such as Advanced Semiconductor Engineering (ASE).[3][4]

Types

Chip scale packages can be classified into the following groups:

  1. Customized leadframe-based CSP (LFCSP)
  2. Flexible substrate-based CSP
  3. Flip-chip CSP (FCCSP)
  4. Rigid substrate-based CSP
  5. Wafer-level redistribution CSP (WL-CSP)

References
  1. "Understanding Flip-Chip and Chip-Scale Package Technologies and Their Applications". Application Note 4002. Maxim Integrated Products. April 18, 2007. Retrieved January 17, 2018.
  2. Puttlitz, Karl J.; Totta, Paul A. (December 6, 2012). Area Array Interconnection Handbook. Springer Science+Business Media. p. 702. ISBN 978-1-4615-1389-6.
  3. Prior, Brandon (January 22, 2001). "Wafer Scale Emerging". EDN. Retrieved March 31, 2016.
  4. "ASE Ramps Wafer Level CSP Production". EDN. October 12, 2001. Retrieved March 31, 2016.
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