Wafer (electronics)

Silicon wafers are available in a variety of diameters from 25.4 mm (1 inch) to 300 mm (11.8 inches).[16][17] Semiconductor fabrication plants, colloquially known as fabs, are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using 300 mm, with a proposal to adopt 450 mm.[18][19] Intel, TSMC and Samsung were separately conducting research to the advent of 450 mm "prototype" (research) fabs, though serious hurdles remain.

2-inch (51 mm), 4-inch (100 mm), 6-inch (150 mm), and 8-inch (200 mm) wafers

Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The tabulated thicknesses relate to when that process was introduced, and are not necessarily correct currently, for example the IBM BiCMOS7WL process is on 8 in wafers, but these are only 200um thick. The weight of the wafer goes up along with its thickness and diameter.

A unit wafer fabrication step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%.[23] Larger diameter wafers allow for more die per wafer.

M1 wafer size (156.75 mm) is in process of phase-out in China as of 2020. A number of nonstandard sizes has arisen, so efforts to produce M10 standard (182 mm) is an ongoing effort. Like semiconductor cousin, driving down costs is main driver despite that purity requirements are completely different.

There is considerable resistance to the 450 mm transition despite the possible productivity improvement, because of concern about insufficient return on investment.[23] There are also issues related to increased inter-die / edge-to-edge wafer variation and additional edge defects. 450mm wafers are expected to cost 4 times as much as 300mm wafers, and equipment costs are expected to rise by 20 to 50%.[24] Higher cost semiconductor fabrication equipment for larger wafers increases the cost of 450 mm fabs (semiconductor fabrication facilities or factories). Lithographer Chris Mack claimed in 2012 that the overall price per die for 450 mm wafers would be reduced by only 10–20% compared to 300 mm wafers, because over 50% of total wafer processing costs are lithography-related. Converting to larger 450 mm wafers would reduce price per die only for process operations such as etch where cost is related to wafer count, not wafer area. Cost for processes such as lithography is proportional to wafer area, and larger wafers would not reduce the lithography contribution to die cost.[25] Nikon planned to deliver 450-mm lithography equipment in 2015, with volume production in 2017.[26][27] In November 2013 ASML paused development of 450-mm lithography equipment, citing uncertain timing of chipmaker demand.[28]

The timeline for 450 mm has not been fixed. In 2012, it was expected that 450mm production would start in 2017, which never realized.[29][30] Mark Durcan, then CEO of Micron Technology, said in February 2014 that he expects 450 mm adoption to be delayed indefinitely or discontinued. "I am not convinced that 450mm will ever happen but, to the extent that it does, it’s a long way out in the future. There is not a lot of necessity for Micron, at least over the next five years, to be spending a lot of money on 450mm. There is a lot of investment that needs to go on in the equipment community to make that happen. And the value at the end of the day – so that customers would buy that equipment – I think is dubious."[31] As of March 2014, Intel Corporation expected 450 mm deployment by 2020 (by the end of this decade).[32] Mark LaPedus of semiengineering.com reported in mid-2014 that chipmakers had delayed adoption of 450 mm "for the foreseeable future." According to this report some observers expected 2018 to 2020, while G. Dan Hutcheson, chief executive of VLSI Research, didn't see 450mm fabs moving into production until 2020 to 2025.[33]

The step up to 300 mm required major changes, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers, partly because a FOUP for 300 mm wafers weighs about 7.5 kilograms[34] when loaded with 25 300 mm wafers where a SMIF weighs about 4.8 kilograms[35][36][20] when loaded with 25 200 mm wafers, thus requiring twice the amount of physical strength from factory workers, and increasing fatigue. 300mm FOUPs have handles so that they can be still be moved by hand. 450mm FOUPs weigh 45 kilograms[37] when loaded with 25 450 mm wafers, thus cranes are necessary to manually handle the FOUPs[38] and handles are no longer present in the FOUP. FOUPs are moved around using material handling systems from Muratec or Daifuku. These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe. On the ramp-up to 450 mm, the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2–4 times longer to cool, and the process time will be double.[39] All told, the development of 450 mm wafers requires significant engineering, time, and cost to overcome.

In order to minimize the cost per die, manufacturers wish to maximize the number of dies that can be made from a single wafer; dies always have a square or rectangular shape due to the constraint of wafer dicing. In general, this is a computationally complex problem with no analytical solution, dependent on both the area of the dies as well as their aspect ratio (square or rectangular) and other considerations such as the width of the scribeline or saw lane, and additional space occupied by alignment and test structures. Note that gross DPW formulas account only for wafer area that is lost because it cannot be used to make physically complete dies; gross DPW calculations do not account for yield loss due to defects or parametric issues.

Wafermap showing fully patterned dies, and partially patterned dies which don't fully lie within the wafer.

Nevertheless, the number of gross die per wafer (DPW) can be estimated starting with the first-order approximation or wafer-to-die area ratio,

${\displaystyle DPW=\left\lfloor {\frac {\pi d^{2}}{4S}}\right\rfloor }$,

where ${\displaystyle d}$ is the wafer diameter (typically in mm) and ${\displaystyle S}$ the size of each die (mm²) including the width of the scribeline ( or in the case of a saw lane, the kerf plus a tolerance). This formula simply states that the number of dies which can fit on the wafer cannot exceed the area of the wafer divided by the area of each individual die. It will always overestimate the true best-case gross DPW, since it includes the area of partially patterned dies which do not fully lie on the wafer surface (see figure). These partially patterned dies don't represent complete ICs, so they cannot be sold as functional parts.

Refinements of this simple formula typically add an edge correction, to account for partial dies on the edge, which in general will be more significant when the area of the die is large compared to the total area of the wafer. In the other limiting case (infinitesimally small dies or infinitely large wafers), the edge correction is negligible.

The correction factor or correction term generally takes one of the forms cited by De Vries:[40]

${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}-{\frac {\displaystyle \pi d}{\sqrt {2S}}}}$ (area ratio - circumference/(die diagonal length))

or ${\displaystyle DPW=\left({\frac {\displaystyle \pi d^{2}}{4S}}\right)\exp(-2{\sqrt {S}}/d)}$ (area ratio scaled by an exponential factor)

or ${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}\left(1-{\frac {\displaystyle 2{\sqrt {S}}}{d}}\right)^{2}}$ (area ratio scaled by a polynomial factor).

Studies comparing these analytical formulas to brute-force computational results show that the formulas can be made more accurate, over practical ranges of die sizes and aspect ratios, by adjusting the coefficients of the corrections to values above or below unity, and by replacing the linear die dimension ${\displaystyle {\sqrt {S}}}$ with ${\displaystyle (H+W)/2}$ (average side length) in the case of dies with large aspect ratio:[40]

${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}-0.58^{*}{\frac {\displaystyle \pi d}{\sqrt {S}}}}$

or ${\displaystyle DPW=\left({\frac {\displaystyle \pi d^{2}}{4S}}\right)\exp(-2.32^{*}{\sqrt {S}}/d)}$

or ${\displaystyle DPW={\frac {\displaystyle \pi d^{2}}{4S}}\left(1-{\frac {\displaystyle 1.16^{*}{\sqrt {S}}}{d}}\right)^{2}}$.

Diamond cubic crystal structure of a silicon unit cell

Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm).[41] When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with (100) or (111) faces being the most common for silicon.[41] Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport.[42] Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

Wafers under 200 mm diameter have flats cut into one or more sides indicating the crystallographic planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200 mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type.[43]

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 10¹³ and 10¹⁶ atoms per cm³ of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type.[44] However, compared with single-crystal silicon's atomic density of 5×10²² atoms per cm³, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum.[45] Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications.[46]