Advanced eXtensible Interface

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Example of FIXED, INCR and WRAP bursts

AXI is a burst-based protocol,[11] meaning that there may be multiple data transfers (or beats) for a single request. This makes it useful in the cases where it is necessary to transfer large amount of data from or to a specific pattern of addresses. In AXI, bursts can be of three types, selected by the signals ARBURST (for reads) or AWBURST (for writes):[12]

• FIXED
• INCR
• WRAP

In FIXED bursts, each beat within the transfer has the same address. This is useful for repeated access at the same memory location, such as when reading or writing a FIFO.

${\displaystyle {\mathit {Address}}={\mathit {StartAddress}}}$

In INCR bursts, on the other hand, each beat has an address equal to the previous one plus the transfer size. This burst type is commonly used to read or write sequential memory areas.

${\displaystyle {\mathit {Address}}_{i}={\mathit {StartAddress}}+{\mathit {i}}\cdot {\mathit {TransferSize}}}$

WRAP bursts are similar to the INCR ones, as each transfer has an address equal to the previous one plus the transfer size. However, with WRAP bursts, if the address of the current beat reaches the "Higher Address boundary", it is reset to the "Wrap boundary":

${\displaystyle {\mathit {Address}}_{i}={\mathit {WrapBoundary}}+({\mathit {StartAddress}}+{\mathit {i}}\cdot {\mathit {TransferSize}})\ \mathrm {mod} \ ({\mathit {BurstLength}}\cdot {\mathit {TransferSize}})}$

with

${\displaystyle {\mathit {WrapBoundary}}=\left\lfloor {\frac {\mathit {StartAddress}}{{\mathit {NumberBytes}}\cdot {\mathit {BurstLength}}}}\right\rfloor \cdot ({\mathit {NumberBytes}}\cdot {\mathit {BurstLength}})}$

Example of an AXI read transaction. The master requests 4 beats (ARLEN + 1[13]) of 4 Bytes each starting from address 0x0 with INCR type. The slave returns 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc, all with the OKAY status. Only the most relevant signals are shown here.

To start a read transaction, the master has to provide on the Read address channel:

• the start address on ARADDR
• the burst type, either FIXED, INCR or WRAP, on ARBURST (if present)
• the burst length on ARLEN (if present).

Additionally, the other auxiliary signals, if present, are used to define more specific transfers.

After the usual ARVALID/ARREADY handshake, the slave has to provide on the Read data channel:

• the data corresponding to the specified address(es) on RDATA
• the status of each beat on RRESP

plus any other optional signals. Each beat of the slave response is done with a RVALID/RREADY handshake and, on the last transfer, the slave has to assert RLAST to inform that no more beats will follow without a new read request.

Example of an AXI write transaction. The master drives 4 beats (AWLEN + 1[13]) of 4 Bytes each starting from address 0x0 with INCR type, writing 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc. The slave returns 'OKAY' as write response for the whole transaction. Only the most relevant signals are shown here.

To start a write operation, the master has to provide both the address information and the data ones.

The address information are provided over the Write address channel, in a similar manner as a read operation:

• the start address has to be provided on AWADDR
• the burst type, either FIXED, INCR or WRAP, on AWBURST (if present)
• the burst length on AWLEN (if present)

and, if present, all the optional signals.

A master has also to provide the data related to the specified address(es) on the Write data channel:

• the data on WDATA
• the "strobe" bits on WSTRB (if present), which conditionally mark the individual WDATA bytes as "valid" or "invalid"

Like in the read path, on the last data word, WLAST has to be asserted by the master.

After the completion of both the transactions, the slave has to send back to the master the status of the write over the Write response channel, by returning the result over the BRESP signal.

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