Comparison of ARMv7-A cores

This is a table comparing microarchitectures which implement the ARM ARMv7-A (A means Application[1]) instruction set architecture and mandatory or optional extensions of it, the last AArch32.

Table

coredecode
width
execution
ports
pipeline
depth
Out-of-order executionFPUpipelined
VFP
FPU
registers
NEON
(SIMD)
big.LITTLE
role
virtualization[2]process
technology
L0
cache
L1
cache
L2
cache
core
configurations
speed
per
core
(DMIPS
/ MHz
)
ARM part number
(in the main ID register)
ARM Cortex-A5 18No VFPv4 (optional)16 × 64-bit64-bit wide (optional) No No 40/28 nm 4–64 KiB / core 1, 2, 4 1.57 0xC05
ARM Cortex-A7 25 [3]8No VFPv4Yes16 × 64-bit64-bit wide LITTLE Yes [4] 40/28 nm 8–64 KiB / coreup to 1 MiB (optional) 1, 2, 4, 8 1.9 0xC07
ARM Cortex-A8 22 [5]13No VFPv3No32 × 64-bit64-bit wide No No 65/55/45 nm 32 KiB + 32 KiB256 or 512 (typical) KiB 1 2.0 0xC08
ARM Cortex-A9 23 [6]8–11 [7]Yes VFPv3 (optional)Yes(16 or 32) × 64-bit64-bit wide (optional) Companion Core No [7] 65/45/40/32/28 nm 32 KiB + 32 KiB1 MiB 1, 2, 4 2.5 0xC09
ARM Cortex-A12 311Yes VFPv4Yes32 × 64-bit128-bit wide No [8] Yes 28nm 32-64 KiB + 32 KiB256 KiB, to 8 MiB 1, 2, 4 3.0 0xC0D
ARM Cortex-A15 38 [3]15/17-25Yes VFPv4Yes32 × 64-bit128-bit wide big Yes [9] 32/28/20 nm 32 KiB + 32 KiB per coreup to 4 MiB per cluster, up to 8 MiB per chip 2, 4, 8 (4×2) 3.5 to 4.01 0xC0F
ARM Cortex-A17 2 [10]11+Yes VFPv4Yes32 × 64-bit128-bit wide big Yes 28nm 32 KiB + 32 KiB per core256 KiB, up to 8 MiB up to 4 4.0 0xC0E
Qualcomm Scorpion 23 [11]10Yes (FXU&LSU only) [12] VFPv3Yes128-bit wide No 65/45 nm 32 KiB + 32 KiB256 KiB (single-core)
512 KiB (dual-core)
1, 2 2.1 0x00F
Qualcomm Krait [13] 3711Yes VFPv4 [14]Yes128-bit wide No 28 nm 4 KiB + 4 KiB direct mapped16 KiB + 16 KiB 4-way set associative1 MiB 8-way set associative (dual-core) / 2 MiB (quad-core) 2, 4 3.3 (Krait 200)
3.39 (Krait 300)
3.39 (Krait 400)
3.51 (Krait 450)
0x04D

0x06F
Apple A6 3512Yes VFPv4Yes32 × 64-bit128-bit wide No 32 nm 32 KiB + 32 KiB1 MiB 2 3.5 ?
core decode
width
execution
ports
pipeline
depth
Out-of-order execution FPU pipelined
VFP
FPU
registers
NEON
(SIMD)
big.LITTLE
role
virtualization[2] process
technology
L0
cache
L1
cache
L2
cache
core
configurations
speed
per
core
(DMIPS
/ MHz
)
ARM part number
(in the main ID register)

See also

References

  1. "ARM V7 Differences". infocenter.arm.com. ARM Information Center. Retrieved 1 June 2016.
  2. "ARM processor hardware virtualization support". www.arm.com. ARM Holdings. Retrieved 1 June 2016.
  3. "big.LITTLE processing with ARM Cortex-A15 & Cortex-A7" (PDF). www.arm.com. ARM Holdings. Archived from the original (PDF) on 17 October 2013. Retrieved 6 August 2014.
  4. "Cortex-A7 processor". www.arm.com. ARM Holdings. Retrieved 1 June 2016.
  5. "Cortex-A8 architecture". processors.wiki.TI.com. Texas Instruments. Archived from the original on 8 August 2014. Retrieved 6 August 2014.
  6. "The ARM Cortex-A9 processors" (PDF). www.arm.com. ARM Holdings. Archived from the original (PDF) on 17 November 2014. Retrieved 6 August 2014.
  7. "Cortex-A9 processor". www.arm.com. ARM Holdings. Retrieved 15 September 2014.
  8. http://community.arm.com/groups/processors/blog/2014/09/30/arm-cortex-a17-cortex-a12-processor-update
  9. "Cortex-A15 processor". www.arm.com. ARM Holdings. Retrieved 9 August 2016.
  10. "ARM Cortex-A17 MPCore processor technical reference manual" (PDF). infocenter.arm.com. ARM Holdings. Retrieved 18 September 2014.
  11. Klug, Brian (7 October 2011). "Qualcomm's new Snapdragon S4: MSM8960 & Krait architecture explored". www.anandtech.com. Anandtech. Retrieved 6 August 2014.
  12. http://rtcgroup.com/arm/2007/presentations/253%20-%20ARM_DevCon_2007_Snapdragon_FINAL_20071004.pdf
  13. http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture
  14. http://www.anandtech.com/show/5559/qualcomm-snapdragon-s4-krait-performance-preview-msm8960-adreno-225-benchmarks/2
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