Semiconductor device fabrication

Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically the metal–oxide–semiconductor (MOS) devices used in the integrated circuit (IC) chips that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is almost always used, but various compound semiconductors are used for specialized applications.

Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future
NASA's Glenn Research Center clean room
External image
Photo of the interior of a clean room of a 300mm fab run by TSMC

The entire manufacturing process, from start to packaged chips ready for shipment, takes six to eight weeks and is performed in highly specialized semiconductor fabrication plants, also called foundries or fabs.[1] All fabrication takes place inside a clean room, which is the central part of a fab. In more advanced semiconductor devices, such as modern 14/10/7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average.[2] Production in advanced fabrication facilities is completely automated and carried out in a hermetically sealed nitrogen environment to improve yield (the percent of microchips that function correctly in a wafer), with automated material handling systems taking care of the transport of wafers from machine to machine. Wafers are transported inside FOUPs, special sealed plastic boxes. All machinery and FOUPs contain an internal nitrogen atmosphere. The air inside the machinery and FOUPs is usually kept cleaner than the surrounding air in the cleanroom. This internal atmosphere is known as a mini-environment.[3] Fabrication plants need large amounts of liquid nitrogen to maintain the atmosphere inside production machinery and FOUPs, which is constantly purged with nitrogen.[4]

Size

A specific semiconductor process has specific rules on the minimum size and spacing for features on each layer of the chip.[5] Often a newer semiconductor processes has smaller minimum sizes and tighter spacing which allow a simple die shrink to reduce costs and improve performance[5] partly due to an increase in transistor density (number of transistors per square millimeter). Early semiconductor processes had arbitrary names such as HMOS III, CHMOS V; later ones are referred to by size such as 90 nm process.

By industry standard, each generation of the semiconductor manufacturing process, also known as technology node or process node,[6] is designated by the process’ minimum feature size. Technology nodes, also known as "process technologies" or simply "nodes", are typically indicated by the size in nanometers (or historically micrometers) of the process' transistor gate length. However, this has not been the case since 1994. Initially transistor gate length was smaller than what the process node name (e.g. 350 nm node) suggested, however this trend reversed in 2009.[7] The nanometers used to name process nodes has become more of a marketing term that has no relation with actual feature sizes nor transistor density (number of transistors per square millimeter). For example, Intel's 10 nm process actually has features (the tips of FinFET fins) with a width of 7 nm, Intel's 10 nm process is similar in transistor density to TSMC's 7 nm processes, while GlobalFoundries' 12 and 14 nm processes have similar feature sizes.[8][9][10]

History
See also: List of semiconductor scale examples, Moore's law, MOS integrated circuit, Semiconductor industry, and Transistor density

20th century

The first metal–oxide–silicon field-effect transistors (MOSFETs) were fabricated by Egyptian engineer Mohamed M. Atalla and Korean engineer Dawon Kahng at Bell Labs between 1959 and 1960.[11] There were originally two types of MOSFET technology, PMOS (p-type MOS) and NMOS (n-type MOS).[12] Both types were developed by Atalla and Kahng when they originally invented the MOSFET, fabricating both PMOS and NMOS devices at 20 µm[11] and 10 µm scales.[13]

An improved type of MOSFET technology, CMOS, was developed by Chih-Tang Sah and Frank Wanlass at Fairchild Semiconductor in 1963.[14][15] CMOS was commercialised by RCA in the late 1960s.[14] RCA commercially used CMOS for its 4000-series integrated circuits in 1968, starting with a 20 µm process before gradually scaling to a 10 µm process over the next several years.[16]

Semiconductor device manufacturing has since spread from Texas and California in the 1960s to the rest of the world, including Asia, Europe, and the Middle East.

21st century

The semiconductor industry is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. Samsung Electronics, the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. Intel, the second-largest manufacturer, has facilities in Europe and Asia as well as the US. TSMC, the world's largest pure play foundry, has facilities in Taiwan, China, Singapore, and the US. Qualcomm and Broadcom are among the biggest fabless semiconductor companies, outsourcing their production to companies like TSMC.[17] They also have facilities spread in different countries.

Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.[18][19][20] For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred.[21] Additionally, TSMC and Samsung's 10 nm processes are only slightly denser than Intel's 14 nm in transistor density. They are actually much closer to Intel's 14 nm process than they are to Intel's 10 nm process (e.g. Samsung's 10 nm processes' fin pitch is the exact same as that of Intel's 14 nm process: 42 nm).[22][23]

As of 2019, 14 nanometer and 10 nanometer chips are in mass production by Intel, UMC, TSMC, Samsung, Micron, SK Hynix, Toshiba Memory and GlobalFoundries, with 7 nanometer process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The 5 nanometer process began being produced by Samsung in 2018.[24] As of 2019, the node with the highest transistor density is TSMC's 5 nanometer N5 node,[25] with a density of 171.3 million transistors per square millimeter.[26] In 2019, Samsung and TSMC announced plans to produce 3 nanometer nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12 nm orders would be beyond the company's financial abilities.[27] As of 2019, Samsung is the industry leader in advanced semiconductor scaling, followed by TSMC and then Intel.[28]

List of steps

This is a list of processing techniques that are employed numerous times throughout the construction of a modern electronic device; this list does not necessarily imply a specific order. Equipment for carrying out these processes is made by a handful of companies. All equipment needs to be tested before a semiconductor fabrication plant is started.[29]

Additionally steps such as Wright etch may be carried out.

Progress of miniaturization, and comparison of sizes of semiconductor manufacturing process nodes with some microscopic objects and visible light wavelengths.

Prevention of contamination and defects
Main article: cleanroom

When feature widths were far greater than about 10 micrometres, semiconductor purity was not as big of an issue as it is today in device manufacturing. As devices become more integrated, cleanrooms must become even cleaner. Today, fabrication plants are pressurized with filtered air to remove even the smallest particles, which could come to rest on the wafers and contribute to defects. The ceilings of semiconductor cleanrooms have fan filter units (FFUs) at regular intervals to constantly replace and filter the air in the cleanroom; semiconductor capital equipment may also have their own FFUs. The FFUs, combined with raised floors with grills, help ensure a laminar air flow, to ensure that particles are immediately brought down to the floor and do not stay suspended in the air due to turbulence. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination. To prevent oxidation and to increase yield, FOUPs and semiconductor capital equipment may have a hermetically sealed pure nitrogen environment with ISO class 1 level of dust. FOUPs and SMIF pods isolate the wafers from the air in the cleanroom, increasing yield because they reduce the number of defects caused by dust particles. Also, Fabs have as few people as possible in the cleanroom to make maintaining the cleanroom environment easier, since people, even when wearing cleanroom suits, shed large amounts of particles, especially when walking.[36][37][38]

Wafers
Main articles: Wafer (electronics) and mono-crystalline silicon

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 300 mm (slightly less than 12 inches) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Processing
See also: Wafer fabrication

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

Modern chips have up to eleven or more metal levels produced in over 300 or more sequenced processing steps.

Front-end-of-line (FEOL) processing
Main article: FEOL

FEOL processing refers to the formation of the transistors directly in the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a straining step wherein a silicon variant such as silicon-germanium (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called silicon on insulator technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.

Gate oxide and implants
Main articles: self-aligned gate and doping (semiconductor)

Front-end surface engineering is followed by growth of the gate dielectric (traditionally silicon dioxide), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In dynamic random-access memory (DRAM) devices, storage capacitors are also fabricated at this time, typically stacked above the access transistor (the now defunct DRAM manufacturer Qimonda implemented these capacitors with trenches etched deep into the silicon surface).

Back-end-of-line (BEOL) processing
Main article: BEOL

Metal layers

Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL (not to be confused with back end of chip fabrication, which refers to the packaging and testing stages). BEOL processing involves creating metal interconnecting wires that are isolated by dielectric layers. The insulating material has traditionally been a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used (such as silicon oxycarbide), typically providing dielectric constants around 2.7 (compared to 3.82 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers. High-κ dielectrics may instead be used.

Interconnect
Main article: interconnect (integrated circuits)
Synthetic detail of a standard cell through four layers of planarized copper interconnect, down to the polysilicon (pink), wells (greyish) and substrate (green).

Historically, the metal wires have been composed of aluminum. In this approach to wiring (often called subtractive aluminum), blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes (called "vias") in the insulating material and then depositing tungsten in them with a CVD technique using tungsten hexafluoride; this approach is still used in the fabrication of many memory chips such as dynamic random-access memory (DRAM), because the number of interconnect levels is small (currently no more than four).

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become so significant as to prompt a change in wiring material (from aluminum to copper interconnect layer) and a change in dielectric material (from silicon dioxides to newer low-K insulators). This performance enhancement also comes at a reduced cost via damascene processing, which eliminates processing steps. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked, extending outside the depth of focus of available lithography, and thus interfering with the ability to pattern. CMP (chemical-mechanical planarization) is the primary processing method to achieve such planarization, although dry etch back is still sometimes employed when the number of interconnect levels is no more than three. Copper interconnects use an electrically conductive barrier layer to prevent the copper from diffusing into ("poisoning") its surroundings.

Wafer test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. For example, thin film metrology based on ellipsometry or reflectometry is used to tightly control the thickness of gate oxide, as well as the thickness, refractive index and extinction coefficient of photoresist and other coatings. Wafer test metrology equipment is used to verify that the wafers haven't been damaged by previous processing steps up until testing; if too many dies on one wafer have failed, the entire wafer is scrapped to avoid the costs of further processing. Virtual metrology has been used to predict wafer properties based on statistical methods without performing the physical measurement itself.[1]

Device test
Main article: Wafer testing

Once the front-end process has been completed, the semiconductor devices or chips are subjected to a variety of electrical tests to determine if they function properly. The percent of devices on the wafer found to perform properly is referred to as the yield. Manufacturers are typically secretive about their yields, but it can be as low as 30%, meaning that only 30% of the chips on the wafer work as intended. Process variation is one among many reasons for low yield.[40] Testing is carried out to prevent chips from being assembled into relatively expensive packages.

The yield is often but not necessarily related to device (die or chip) size. As an example, In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2. The yield went down to 32.0% with an increase in die size to 100 mm2.[41]

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. Currently, electronic dye marking is possible if wafer test data (results) are logged into a central computer database and chips are "binned" (i.e. sorted into virtual bins) according to predetermined test limits such as maximum operating frequencies/clocks, number of working (fully functional) cores per chip, etc. The resulting binning data can be graphed, or logged, on a wafer map to trace manufacturing defects and mark bad chips. This map can also be used during wafer assembly and packaging. Binning allows chips that would otherwise be rejected to be reused in lower-tier products, as is the case with GPUs and CPUs, increasing device yield, especially since very few chips are fully functional (have all cores functioning correctly, for example). eFUSEs may be used to disconnect parts of chips such as cores, either because they didn't work as intended during binning, or as part of market segmentation (using the same chip for low, mid and high-end tiers). Chips may have spare parts to allow the chip to fully pass testing even if it has several non-working parts.

Chips are also tested again after packaging, as the bond wires may be missing, or analog performance may be altered by the package. This is referred to as the "final test". Chips may also be imaged using x-rays.

Usually, the fab charges for testing time, with prices in the order of cents per second. Testing times vary from a few milliseconds to a couple of seconds, and the test software is optimized for reduced testing time. Multiple chip (multi-site) testing is also possible because many testers have the resources to perform most or all of the tests in parallel and on several chips at once.

Chips are often designed with "testability features" such as scan chains or a "built-in self-test" to speed testing and reduce testing costs. In certain designs that use specialized analog fab processes, wafers are also laser-trimmed during testing, in order to achieve tightly distributed resistance values as specified by the design.

Good designs try to test and statistically manage corners (extremes of silicon behavior caused by a high operating temperature combined with the extremes of fab processing steps). Most designs cope with at least 64 corners.

Device yield

Device yield or die yield is the number of working chips or dies on a wafer, given in percentage since the number of chips on a wafer (Die per wafer, DPW) can vary depending on the chips' size and the wafer's diameter. Yield degradation is a reduction in yield, which historically was mainly caused by dust particles, however since the 1990s, yield degradation is mainly caused by process variation, the process itself and by the tools used in chip manufacturing, although dust still remains a problem in many older fabs. Dust particles have an increasing effect on yield as feature sizes are shrunk with newer processes. Automation and the use of mini environments inside of production equipment, FOUPs and SMIFs have enabled a reduction in defects caused by dust particles. Device yield must be kept high to reduce the selling price of the working chips since working chips have to pay for those chips that failed, and to reduce the cost of wafer processing. Yield can also be affected by the design and operation of the fab.

Tight control over contaminants and the production process are necessary to increase yield. Contaminants may be chemical contaminants or be dust particles. "Killer defects" are those caused by dust particles that cause complete failure of the device (such as a transistor). There are also harmless defects. A particle needs to be 1/5 the size of a feature to cause a killer defect. So if a feature is 100 nm across, a particle only needs to be 20 nm across to cause a killer defect. Electrostatic electricity can also affect yield adversely. Chemical contaminants or impurities include heavy metals such as Iron, Copper, Nickel, Zinc, Chromium, Gold, Mercury and Silver, alkali metals such as Sodium, Potassium and Lithium, and elements such as Aluminum, Magnesium, Calcium, Chlorine, Sulfur, Carbon, and Fluorine. It is important for those elements to not remain in contact with the silicon, as they could reduce yield. Chemical mixtures may be used to remove those elements from the silicon; different mixtures are effective against different elements.

Several models are used to estimate yield. Those are Murphy's model, Poisson's model, the binomial model, Moore's model and Seeds' model. There is no universal model; a model has to be chosen based on actual yield distribution (the location of defective chips) For example, Murphy's model assumes that yield loss occurs more at the edges of the wafer (non-working chips are concentrated on the edges of the wafer), Poisson's model assumes that defective dies are spread relatively evenly across the wafer, and Seeds's model assumes that defective dies are clustered together.[42]

Smaller dies cost less to produce (since more fit on a wafer, and wafers are processed and priced as a whole), and can help achieve higher yields since smaller dies have a lower chance of having a defect. However, smaller dies require smaller features to achieve the same functions of larger dies or surpass them, and smaller features require reduced process variation and increased purity (reduced contamination) to maintain high yields. Metrology tools are used to inspect the wafers during the production process and predict yield, so wafers predicted to have too many defects may be scrapped to save on processing costs.[43]

Die preparation
Main articles: Wafer backgrinding and Die preparation

Once tested, a wafer is typically reduced in thickness in a process also known as "backlap",[44] "backfinish" or "wafer thinning"[45] before the wafer is scored and then broken into individual dies, a process known as wafer dicing. Only the good, unmarked chips are packaged.

Packaging
Main article: Integrated circuit packaging

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny bondwires are used to connect the pads to the pins. In the old days, wires were attached by hand, but now specialized machines perform the task. Traditionally, these wires have been composed of gold, leading to a lead frame (pronounced "leed frame") of solder-plated copper; lead is poisonous, so lead-free "lead frames" are now mandated by RoHS.

Chip scale package (CSP) is another packaging technology. A plastic dual in-line package, like most packages, is many times larger than the actual die hidden inside, whereas CSP chips are nearly the size of the die; a CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser then etches the chip's name and numbers on the package.

Hazardous materials
See also: Health hazards in semiconductor manufacturing occupations

Many toxic materials are used in the fabrication process.[46] These include:

It is vital that workers should not be directly exposed to these dangerous substances. The high degree of automation common in the IC fabrication industry helps to reduce the risks of exposure. Most fabrication facilities employ exhaust management systems, such as wet scrubbers, combustors, heated absorber cartridges, etc., to control the risk to workers and to the environment.

Timeline of MOSFET demonstrations
This section is an excerpt from List of semiconductor scale examples § Timeline of MOSFET demonstrations[edit]

PMOS and NMOS

MOSFET (PMOS and NMOS) demonstrations
Date Channel length Oxide thickness[47] MOSFET logic Researcher(s) Organization Ref
June 1960 20,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [48][49]
NMOS
10,000 nm 100 nm PMOS Mohamed M. Atalla, Dawon Kahng Bell Telephone Laboratories [50]
NMOS
May 1965 8,000 nm 150 nm NMOS Chih-Tang Sah, Otto Leistiko, A.S. Grove Fairchild Semiconductor [51]
5,000 nm 170 nm PMOS
December 1972 1,000 nm ? PMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu IBM T.J. Watson Research Center [52][53][54]
1973 7,500 nm ? NMOS Sohichi Suzuki NEC [55][56]
6,000 nm ? PMOS ? Toshiba [57][58]
October 1974 1,000 nm 35 nm NMOS Robert H. Dennard, Fritz H. Gaensslen, Hwa-Nien Yu IBM T.J. Watson Research Center [59]
500 nm
September 1975 1,500 nm 20 nm NMOS Ryoichi Hori, Hiroo Masuda, Osamu Minato Hitachi [53][60]
March 1976 3,000 nm ? NMOS ? Intel [61]
April 1979 1,000 nm 25 nm NMOS William R. Hunter, L. M. Ephrath, Alice Cramer IBM T.J. Watson Research Center [62]
December 1984 100 nm 5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, K. Kiuchi Nippon Telegraph and Telephone [63]
December 1985 150 nm 2.5 nm NMOS Toshio Kobayashi, Seiji Horiguchi, M. Miyake, M. Oda Nippon Telegraph and Telephone [64]
75 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [65]
January 1986 60 nm ? NMOS Stephen Y. Chou, Henry I. Smith, Dimitri A. Antoniadis MIT [66]
June 1987 200 nm 3.5 nm PMOS Toshio Kobayashi, M. Miyake, K. Deguchi Nippon Telegraph and Telephone [67]
December 1993 40 nm ? NMOS Mizuki Ono, Masanobu Saito, Takashi Yoshitomi Toshiba [68]
September 1996 16 nm ? PMOS Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [69]
June 1998 50 nm 1.3 nm NMOS Khaled Z. Ahmed, Effiong E. Ibok, Miryeong Song Advanced Micro Devices (AMD) [70][71]
December 2002 6 nm ? PMOS Bruce Doris, Omer Dokumaci, Meikei Ieong IBM [72][73][74]
December 2003 3 nm ? PMOS Hitoshi Wakabayashi, Shigeharu Yamagami NEC [75][73]
NMOS

CMOS (single-gate)

Complementary MOSFET (CMOS) demonstrations (single-gate)
Date Channel length Oxide thickness[47] Researcher(s) Organization Ref
February 1963 ? ? Chih-Tang Sah, Frank Wanlass Fairchild Semiconductor [76][77]
1968 20,000 nm 100 nm ? RCA Laboratories [78]
1970 10,000 nm 100 nm ? RCA Laboratories [78]
December 1976 2,000 nm ? A. Aitken, R.G. Poulsen, A.T.P. MacArthur, J.J. White Mitel Semiconductor [79]
February 1978 3,000 nm ? Toshiaki Masuhara, Osamu Minato, Toshio Sasaki, Yoshio Sakai Hitachi Central Research Laboratory [80][81][82]
February 1983 1,200 nm 25 nm R.J.C. Chwang, M. Choi, D. Creek, S. Stern, P.H. Pelley Intel [83][84]
900 nm 15 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [83][85]
December 1983 1,000 nm 22.5 nm G.J. Hu, Yuan Taur, Robert H. Dennard, Chung-Yu Ting IBM T.J. Watson Research Center [86]
February 1987 800 nm 17 nm T. Sumi, Tsuneo Taniguchi, Mikio Kishimoto, Hiroshige Hirano Matsushita [83][87]
700 nm 12 nm Tsuneo Mano, J. Yamada, Junichi Inoue, S. Nakajima Nippon Telegraph and Telephone (NTT) [83][88]
September 1987 500 nm 12.5 nm Hussein I. Hanafi, Robert H. Dennard, Yuan Taur, Nadim F. Haddad IBM T.J. Watson Research Center [89]
December 1987 250 nm ? Naoki Kasai, Nobuhiro Endo, Hiroshi Kitajima NEC [90]
February 1988 400 nm 10 nm M. Inoue, H. Kotani, T. Yamada, Hiroyuki Yamauchi Matsushita [83][91]
December 1990 100 nm ? Ghavam G. Shahidi, Bijan Davari, Yuan Taur, James D. Warnock IBM T.J. Watson Research Center [92]
1993 350 nm ? ? Sony [93]
1996 150 nm ? ? Mitsubishi Electric
1998 180 nm ? ? TSMC [94]
December 2003 5 nm ? Hitoshi Wakabayashi, Shigeharu Yamagami, Nobuyuki Ikezawa NEC [75][95]

Multi-gate MOSFET (MuGFET)

Multi-gate MOSFET (MuGFET) demonstrations
Date Channel length MuGFET type Researcher(s) Organization Ref
August 1984 ? DGMOS Toshihiro Sekigawa, Yutaka Hayashi Electrotechnical Laboratory (ETL) [96]
1987 2,000 nm DGMOS Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [97]
December 1988 250 nm DGMOS Bijan Davari, Wen-Hsing Chang, Matthew R. Wordeman, C.S. Oh IBM T.J. Watson Research Center [98][99]
180 nm
? GAAFET Fujio Masuoka, Hiroshi Takato, Kazumasa Sunouchi, N. Okabe Toshiba [100][101][102]
December 1989 200 nm FinFET Digh Hisamoto, Toru Kaga, Yoshifumi Kawamoto, Eiji Takeda Hitachi Central Research Laboratory [103][104][105]
December 1998 17 nm FinFET Digh Hisamoto, Chenming Hu, Tsu-Jae King Liu, Jeffrey Bokor University of California (Berkeley) [106][107]
2001 15 nm FinFET Chenming Hu, Yang‐Kyu Choi, Nick Lindert, Tsu-Jae King Liu University of California (Berkeley) [106][108]
December 2002 10 nm FinFET Shibly Ahmed, Scott Bell, Cyrus Tabery, Jeffrey Bokor University of California (Berkeley) [106][109]
June 2006 3 nm GAAFET Hyunjin Lee, Yang-kyu Choi, Lee-Eun Yu, Seong-Wan Ryu KAIST [110][111]

Other types of MOSFET

MOSFET demonstrations (other types)
Date Channel
length
(nm)		 Oxide
thickness
(nm)[47]		 MOSFET
type		 Researcher(s) Organization Ref
October 1962 ? ? TFT Paul K. Weimer RCA Laboratories [112][113]
1965 ? ? GaAs H. Becke, R. Hall, J. White RCA Laboratories [114]
October 1966 100,000 100 TFT T.P. Brody, H.E. Kunig Westinghouse Electric [115][116]
August 1967 ? ? FGMOS Dawon Kahng, Simon Min Sze Bell Telephone Laboratories [117]
October 1967 ? ? MNOS H.A. Richard Wegener, A.J. Lincoln, H.C. Pao Sperry Corporation [118]
July 1968 ? ? BiMOS Hung-Chang Lin, Ramachandra R. Iyer Westinghouse Electric [119][120]
October 1968 ? ? BiCMOS Hung-Chang Lin, Ramachandra R. Iyer, C.T. Ho Westinghouse Electric [121][120]
1969 ? ? VMOS ? Hitachi [122][123]
September 1969 ? ? DMOS Y. Tarui, Y. Hayashi, Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [124][125]
October 1970 ? ? ISFET Piet Bergveld University of Twente [126][127]
October 1970 1000 ? DMOS Y. Tarui, Y. Hayashi, Toshihiro Sekigawa Electrotechnical Laboratory (ETL) [128]
1977 ? ? VDMOS John Louis Moll HP Labs [122]
? ? LDMOS ? Hitachi [129]
July 1979 ? ? IGBT Bantval Jayant Baliga, Margaret Lazeri General Electric [130]
December 1984 2000 ? BiCMOS H. Higuchi, Goro Kitsukawa, Takahide Ikeda, Y. Nishio Hitachi [131]
May 1985 300 ? ? K. Deguchi, Kazuhiko Komatsu, M. Miyake, H. Namatsu Nippon Telegraph and Telephone [132]
February 1985 1000 ? BiCMOS H. Momose, Hideki Shibata, S. Saitoh, Jun-ichi Miyamoto Toshiba [133]
November 1986 90 8.3 ? Han-Sheng Lee, L.C. Puzio General Motors [134]
December 1986 60 ? ? Ghavam G. Shahidi, Dimitri A. Antoniadis, Henry I. Smith MIT [135][66]
May 1987 ? 10 ? Bijan Davari, Chung-Yu Ting, Kie Y. Ahn, S. Basavaiah IBM T.J. Watson Research Center [136]
December 1987 800 ? BiCMOS Robert H. Havemann, R. E. Eklund, Hiep V. Tran Texas Instruments [137]
June 1997 30 ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [138]
1998 32 ? ? ? NEC [73]
1999 8
April 2000 8 ? EJ-MOSFET Hisao Kawaura, Toshitsugu Sakamoto, Toshio Baba NEC [139]

Timeline of commercial MOSFET nodes
Main articles: List of semiconductor scale examples and Transistor density

See also

References
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Further reading
  • Kaeslin, Hubert (2008), Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication, Cambridge University Press, section 14.2.
  • Wiki related to Chip Technology
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