OpenCores

Damjan Lampret, one of the founders of OpenCores, stated on his website that it began in 1999.[7] The first public record of the new website and its objectives was in EE Times in 2000.[8] Then CNET News reported in 2001.[9] Through the following years it was supported by advertising and sponsorship, including by Flextronics.[1]

In mid-2007 an appeal was put out for a new backer,[10] and that November, Swedish design house ORSoC AB[11] agreed to take over maintenance of the OpenCores website.[12]

EE Times reported in late 2008 that OpenCores had passed the 20,000 subscriber mark.[13] In October 2010 it reached 95,000 registered users and had approximately 800 projects. In July 2012 it reached 150,000 registered users.

During 2015, ORSoC AB formed a joint venture with KNCMiner AB to develop bitcoin mining machines. As this became the primary focus of the business, they were able to spend less time with the opencores.org project. In response to the growing lack of commitment, the core OpenRISC development team set up the Free and Open Source Silicon Foundation (FOSSi), and registered the libreCores.org website as the basis for all future development, independent of commercial control.[14]

In the absence of a widely accepted open source hardware license, the components produced by the OpenCores initiative use several different software licenses. The most common is the GNU LGPL, which states that any modifications to a component must be shared with the community, while one can still use it together with proprietary components. The less restrictive 3-clause BSD license is also used in some hardware projects, while the GNU GPL is often used for software components, such as models and firmware.

The library will consist of design elements from central processing units, memory controllers, peripherals, motherboards, and other components. Emerging semiconductor manufacturers could use the information and license designs for free.

The emphasis is on digital modules called "cores", commonly known as IP Cores. The components are used for creating both custom integrated circuits (ASICs) and FPGAs.

The cores are implemented in the hardware description languages Verilog, VHDL or SystemC which may be synthesized to either silicon or gate arrays.

The project aims at using a common non-proprietary system bus named Wishbone, and most components are nowadays adapted to this bus.

Among the components created by OpenCores contributors are:

• OpenRISC – a highly configurable RISC central processing unit
• Amber (processor core) – an ARM-compatible RISC central processing unit
• A Zilog Z80 clone
• USB 2.0 controller
• Tri Ethernet controller, 10/100/1000 Mbit
• Encryption units, for example DES, AES and RSA
• HyperTransport Tunnel
• A PIC16F84 core[15]
• Zet – an x86 compatible core[16]

In April 2011 OpenCores opened donations[17] for a new project to develop a complete system on a chip design based on the OpenRISC processor and implement it into an ASIC-component. OpenCores affiliated with OpenCores, for example OpenSPARC and LEON.

• Free and Open Source Silicon Foundation
• Free content
• Open content
• Open-source hardware
• Wishbone

• Official website
• Greenbaum, Eli (2011). "Open Source Semiconductor Core Licensing" (PDF). Harvard Journal of Law & Technology (JOLT). Harvard. 25 (1): 131–157.