Penryn (microarchitecture)

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45 nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P), Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771 based MCMs with two or four active Wolfdale cores.

Penryn
General information
LaunchedApril 2008 (April 2008)
Performance
Max. CPU clock rate1.06 GHz to 3.33 GHz
FSB speeds533 MT/s to 1600 MT/s
Cache
L1 cache64 KB per core
L2 cache3 MB to 12 MB unified
L3 cache8 MB to 16 MB shared (Xeon)
Architecture and classification
ArchitectureIntel Core x86
Instructionsx86, x86-64
Extensions
Physical specifications
Transistors
Cores
  • 1-4 (2-6 Xeon)
Socket(s)
Products, models, variants
Model(s)
  • P6 Family (Celeron, Pentium, Pentium Dual-Core, Core 2 range, Xeon)
History
PredecessorCore
SuccessorNehalem

Architectural improvements over 65-nanometer Core 2 CPUs include a new divider with reduced latency, a new shuffle engine, and SSE4.1 instructions (some of which are enabled by the new single-cycle shuffle engine).[1]

Maximum L2 cache size per chip was increased from 4 to 6 MB, with L2 associativity increased from 16-way to 24-way. Cut-down versions with 3 MB L2 also exist, which are commonly called Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn, listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with only one active core.

CPU List

ProcessorBrand nameModel (list)CoresL2 CacheSocketTDP
Penryn-L Core 2 Solo SU3xxx13 MiBBGA9565.5 W
Penryn-3M Core 2 Duo SU7xxx23 MBBGA95610 W
SU9xxx
Penryn SL9xxx6 MiB17 W
SP9xxx25/28 W
Penryn-3M P7xxx3 MiBSocket P
FCBGA6
25 W
P8xxx
Penryn P9xxx6 MiB
Penryn-3M T6xxx2 MiB35 W
T8xxx3 MiB
Penryn T9xxx6 MiB
E8x356 MiBSocket P35-55 W
Penryn-QC Core 2 Quad Q9xxx42x3-2x6 MiBSocket P45 W
Penryn XE Core 2 Extreme X9xxx26 MiBSocket P44 W
Penryn-QC QX9xxx42x6 MiB45 W
Penryn-3M Celeron T3xxx21 MiBSocket P35 W
SU2xxxµFC-BGA 95610 W
Penryn-L 9x011 MiBSocket P35 W
7x3µFC-BGA 95610 W
Penryn-3M Pentium T4xxx21 MiBSocket P35 W
SU4xxx2 MiBµFC-BGA 95610 W
Penryn-L SU2xxx15.5 W
Wolfdale-3M
Celeron E3xxx21 MBLGA 77565 W
Pentium E2210
E5xxx2 MB
E6xxx
Core 2 Duo E7xxx3 MB
Wolfdale E8xxx6 MB
Xeon 31x045-65 W
Wolfdale-CL 30x41LGA 77130 W
31x3265 W
Yorkfield Xeon X33x042×3–2×6 MBLGA 77565–95 W
Yorkfield-CL X33x3LGA 77180 W
Yorkfield-6M Core 2 Quad Q8xxx2×2 MBLGA 77565–95 W
Q9x0x2×3 MB
Yorkfield Q9x5x2×6 MB
Yorkfield XE Core 2 Extreme QX9xxx2×6 MB130–136 W
QX9xx5LGA 771150 W
Wolfdale-DP Xeon E52xx 2 6 MB LGA 771 65 W
L52xx 20-55 W
X52xx 80 W
Harpertown E54xx 4 2×6 MB LGA 771 80 W
L54xx 40-50 W
X54xx 120-150 W

Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and socket; each combination of these has a unique code name and product code that is used across a number of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each with different sets of features enabled. Most of the mobile and desktop processors come in two variants that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared by processors with different dies, but the specific information about which one is used can be derived from the stepping.

fabcoresMobileDesktop, UP ServerCL ServerDP ServerMP Server
Single-Core 45 nm 45 nm1 Penryn-L
80585
Wolfdale-CL
80588
Dual-Core 45 nm 45 nm2 Penryn-3M
80577
Penryn
80576
Wolfdale-3M
80571
Wolfdale
80570
Wolfdale-CL
80588
Wolfdale-DP
80573
Quad-Core 45 nm 45 nm4 Penryn-QC
80581
Yorkfield-6M
80580
Yorkfield
80569
Yorkfield-CL
80584
Harpertown
80574
Dunnington QC
80583
Six-Core 45 nm 45 nm6 Dunnington
80582

Steppings using 45 nm process

Mobile (Penryn) Desktop (Wolfdale) Desktop (Yorkfield) Server (Wolfdale-DP, Harpertown, Dunnington)
Stepping Released Area CPUID L2 cache Max. clock CeleronPentiumCore 2 CeleronPentiumCore 2Xeon Core 2Xeon Xeon
C0 Nov 2007107 mm²106766 MiB3.00 GHz E8000 P7000 T8000 T9000 P9000 SP9000 SL9000 X9000 E80003100 QX9000 5200 5400
M0 Mar 200882 mm²106763 MiB2.40 GHz 7xx SU3000 P7000 P8000 T8000 SU9000 E5000 E2000 E7000
C1 Mar 2008107 mm²106776 MiB3.20 GHz Q9000 QX9000 3300
M1 Mar 200882 mm²106773 MiB2.50 GHz Q8000 Q9000 3300
E0 Aug 2008107 mm²1067A6 MiB3.33 GHz T9000 P9000 SP9000 SL9000 Q9000 QX9000 E8000 3100 Q9000 Q9000S QX9000 3300 5200 5400
R0 Aug 200882 mm²1067A3 MiB2.93 GHz 7xx 900 SU2000 T3000T4000 SU2000 SU4000SU3000 T6000 SU7000 P8000 SU9000 E3000E5000 E6000 E7000 Q8000 Q8000S Q9000 Q9000S 3300
A1 Sep 2008503 mm²106D13 MiB2.67 GHz 7400

In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2 cache at the same time, and giving them identical cpuid values. All steppings have the new SSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.

Model 29 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores, which leads to an unusually large die size of 503 mm².[2] As of February 2008, it has only found its way into the very high-end Xeon 7400 series (Dunnington).

Roadmap

See also

References

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