Tick–tock model

Tick–tock was a production model adopted in 2007 by chip manufacturer Intel. Under this model, every microarchitecture change (tock) was followed by a die shrink of the process technology (tick). It was replaced by the process–architecture–optimization model, which was announced in 2016 and is like a tick–tock cycle followed by an optimization phase. As a general engineering model, tick-tock is a model that refreshes one side of a binary system each release cycle.

History

Every "tick" represented a shrinking of the process technology of the previous microarchitecture (sometimes introducing new instructions, as with Broadwell, released in late 2014) and every "tock" designated a new microarchitecture.[1] These occurred roughly every year to 18 months.[2] In 2014, Intel created a "tock refresh" of a tock in the form of a smaller update to the microarchitecture[3] not considered a new generation in and of itself.

In March 2016, Intel announced in a Form 10-K report that it deprecated the tick–tock cycle in favor of a three-step process–architecture–optimization model, under which three generations of processors are produced under a single manufacturing process, with the third generation out of three focusing on optimization.[4] The first optimization of the Skylake architecture was Kaby Lake. Intel then announced a second optimization, Coffee Lake,[5] making a total of four generations at 14 nm.[6]

Roadmap
Change
(step)		 Fabri­cation
process		 Micro-
architecture		 Code names
for step		 Intel
Generation
Desktop		 Intel
Generation
Xeon		 Intel Microcode
shortcut(s)
Desktop/WS[7][8]		 Intel Microcode
shortcut(s)
Xeon/Server		 Release
date		 Processors
8P/4P Server 4P/2P Server/WS Embedded Xeon 1P Xeon Enthusiast/​WS Desktop Mobile
Tick
(new fabrica-
tion process)		 65 nm P6, NetBurst Presler,
Cedar Mill,
Yonah		 1995-11-1 (P6),
2000-11-20 (Netburst)		 Presler Cedar Mill Yonah
Tock
(new micro-
architecture)		 Core Merom[9] 2006-07-27[10][11] Tigerton Woodcrest
Clovertown		 Kentsfield Conroe Merom
Tick 45 nm Penryn 2007-11-11[12] Dunnington Harpertown Yorkfield Wolfdale Penryn
Tock Nehalem Nehalem 1 N/A NHM[13] 2008-11-17[14] Beckton Gainestown Lynnfield Bloomfield Lynnfield Clarksfield
Tick 32 nm Westmere 1 N/A WSM[13] 2010-01-04[15][16] Westmere-EX Westmere-EP Gulftown Clarkdale Arrandale
Tock Sandy Bridge Sandy Bridge 2 1 SNB JKT (Jaketown) 2011-01-09[17] (Skipped)[18] Sandy Bridge-EP Gladden Sandy Bridge Sandy Bridge-E Sandy Bridge Sandy Bridge-M
Tick 22 nm[19] Ivy Bridge 3 2 IVB IVT (Ivytown) 2012-04-29 Ivy Bridge-EX[20] Ivy Bridge-EP[20] Gladden Ivy Bridge Ivy Bridge-E[21] Ivy Bridge Ivy Bridge-M
Tock Haswell Haswell 4 3 HSW, CRW (Crystal Well)
with Iris Pro[22][23]		 HSX 2013-06-02 Haswell-EX Haswell-EP N/A Haswell-DT Haswell-E Haswell-DT[24] Haswell-MB (notebooks)
Haswell-LP (ultrabooks)[24]
Refresh Haswell Refresh,
Devil's Canyon[25]		 4 N/A HSW, CRW (Crystal Well)
with Iris Pro[22][23]		 2014-05-11,
2014-06-02		 No server version released Devil's Canyon No mobile version
released
Tick 14 nm[19] Broadwell[26] 5 4 BDW BDX 2014-09-05 Broadwell-EX[27] Broadwell-EP[27] Broadwell-DE Broadwell-DT Broadwell-E Broadwell-DT Broadwell-H
Broadwell-U
Broadwell-Y
Tock Skylake[26] Skylake[26] 6 5 SKL SKX 2015-08-05[28] Skylake-SP Skylake-DE Skylake-DT/H Skylake-X Skylake Skylake-H
Skylake-U
Skylake-Y
Optimizations
(refreshes)
[4][29][30][31]		 Kaby Lake[32] 7 6 KBL 2017-01-03[33] Only 1P server (Xeon E3) version released Kaby Lake-DT/H
cores: 4 (4/8)		 Kaby Lake-X[34] Kaby Lake Kaby Lake-H
Kaby Lake-U
Kaby Lake-Y
Kaby Lake R[35][36] 8 N/A KBL-R 2017-08-21[36] Only mobile version released Kaby Lake R
Coffee Lake 8, 9[37] E-2xxx CFL 2017-10-05[38] Cascade Lake-SP
Cooper Lake (Q2'20)		 Cascade Lake-AP Coffee Lake-DT/H
cores: 6 (12)		 Skylake-X Refresh Coffee Lake-S
Coffee Lake-R		 Coffee Lake-H
Coffee Lake-U
Coffee Lake-H Refresh
Whiskey Lake,
Amber Lake[39]		 8 N/A WHL
AML		 2018-08-28[39] Only mobile version released Whiskey Lake-U
Amber Lake-Y
Comet Lake[40] 10 N/A CML 2019-08-21[40] No server version released Comet Lake-W Comet Lake-S Comet Lake-H
Comet Lake-U
Process Cannon Lake 8 N/A CNL 2018-05-16[41] Only mobile version released Cannon Lake-U
Architecture Cypress Cove[42] Rocket Lake[42] 12 N/A N/A 1Q21 Rocket Lake
10 nm[43] Sunny Cove Ice Lake[44] 10 ICL 2019-08-01[45] Ice Lake-SP (1H21)[46] Ice Lake-U
Ice Lake-Y
Optimization[31] Tiger Lake[31] 11 N/A TGL 2020-09-02[47] Only mobile version released Tiger Lake-H35
Tiger Lake-UP3
Tiger Lake-UP4
Process Sapphire Rapids[48] Sapphire Rapids (2021)
Architecture 7 nm[43] Granite Rapids
Optimization
Process
Architecture 5 nm[43]
Optimization

Atom roadmap

Atom roadmap[49]
Fabri­cation
process		 Micro-
architecture
(Abbr.)[13]		 Code names
for step		 Release
date		 Processors/SoCs
MID, Smartphone Tablet Netbook Nettop Embedded Server Communication CE
Tick 45 nm Bonnell
(BNL)		 Bonnell ? 2008 Silverthorne N/A Diamondville Tunnel Creek & Stellarton N/A Sodaville
Tock Bonnell ? 2010 Lincroft Pineview Groveland
Tick 32 nm Saltwell 2011 Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview) Clover Trail (Cloverview) Cedar Trail (Cedarview) Un­known Centerton & Briarwood Un­known Berryville
Tick 22 nm Silvermont
(SLM)		 Silvermont 2013 Merrifield (Tangier)[50] & Moorefield (Anniedale)[51] & Slayton Bay Trail-T (Valleyview) Bay Trail-M (Valleyview) Bay Trail-D (Valleyview) Bay Trail-I (Valleyview) Avoton Rangeley Un­known
Tick 14 nm[49] Airmont 2014 Binghamton & Riverton Cherry Trail-T (Cherryview)[52] Braswell[53] Denverton
Cancelled		 Un­known Un­known
Tock Goldmont[54]
(GLM)		 Goldmont 2016 Broxton Cancelled Broxton Cancelled
Apollo Lake		 Apollo Lake Apollo Lake Un­known Denverton Un­known Un­known

Note: There is further the Xeon Phi. It has up to now undergone four development steps with a current top model that got the code name Knights Landing (shortcut: KNL;[13] the predecessor code names all had the leading term Knights in their name) that is derived from the Silvermont architecture as used for the Intel Atom series but realized in a shrunk 14 nm (FinFET) technology.[55]

Both

See also

References
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  2. "Intel tick–tock model". intel.com. Intel Corporation. Retrieved 2014-11-02. A yearly product cadence moves the industry forward in a predictable fashion that can be planned in advance.
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  5. "Intel Official News on Twitter". Twitter. Retrieved 2017-04-29.
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  7. Intel Releases Linux CPU Microcodes To fix Meltdown & Spectre Bugs by Lawrence Abrams on January 11, 2018
  8. Linux* Processor Microcode Data File Version 20180312 on 3/12/2018
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  13. https://github.com/gz/rust-x86/blob/master/x86data/perfmon_data/mapfile.csv
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  22. Products formerly Crystal Well at Intel web page
  23. What is Crystalwell? by Matt Egan on OCT 31, 2013 at macworld.com
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  27. Shilov, Anton (August 21, 2015). "Intel to release 22-core Xeon E5 v4 'Broadwell-EP' late in 2015". KitGuru.net. Retrieved July 7, 2017.
  28. Carey, Gabe (July 7, 2015). "The wait for Skylake is almost over, first desktop chips likely to hit August 5". DigitalTrends.com. Retrieved July 7, 2017.
  29. "Intel 14nm Kaby Lake "Skylake Refresh" Platform Detailed – Launching in 2H 2016, 256 MB eDRAM H-Series and 91W K-Series Unveiled". wccftech.com. July 2015. The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher
  30. "Intel Releasing 14nm Kaby Lake Processor in 2016 Ahead of 10nm Cannonlake". legitreviews.com. 2015-07-08. We have long known that Intel was planning a ‘Skylake Refresh’ that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.
  31. Mujtaba, Hassan (January 20, 2016). "Intel's Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech.com. Retrieved July 7, 2017.
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  34. "Intel® Core™ X-series Processors Product Specifications". Intel® ARK (Product Specs). Retrieved 2017-10-05.
  35. Products formerly Kaby Lake R
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  37. "Products formerly Coffee Lake".
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  51. "Import Data and Price of Anniedale". zauba.com. Retrieved July 7, 2017.
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  55. Intel veröffentlicht Xeon Phi mit bis zu 7 Teraflops
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