7 nm process

In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 7 nm process as the MOSFET technology node following the 10 nm node. It is based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology.

Semiconductor
device
fabrication
MOSFET scaling
(process nodes)
Future

Taiwan Semiconductor Manufacturing Company (TSMC) began production of 256 Mbit SRAM memory chips using a 7 nm process in June 2016,[1] before Samsung began mass production of 7 nm devices in 2018.[2] The first mainstream 7 nm mobile processor intended for mass market use, the Apple A12 Bionic, was released at Apple's September 2018 event.[3] Although Huawei announced its own 7 nm processor before the Apple A12 Bionic, the Kirin 980 on August 31, 2018, the Apple A12 Bionic was released for public, mass market use to consumers before the Kirin 980. Both chips are manufactured by TSMC.[4]

AMD has released their "Rome" (Epyc 2) processors for servers and datacenters, which are based on TSMC's 7 nm node[5] and feature up to 64 cores and 128 threads. They have also released their "Matisse" consumer desktop processors with up to 16 cores and 32 threads. However, the I/O die on the Rome multi-chip module (MCM) is fabricated with the GloFo 14 nm process, while the Matisse's I/O die uses the GloFo 12 nm process. The Radeon RX 5000 series is also based on the N7FF process.

History

Technology demos

7 nm scale MOSFETs were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Turkish engineer Omer Dokumaci, Taiwanese engineer Meikei Ieong and Romanian engineer Anda Mocuta fabricated a 6 nm silicon-on-insulator (SOI) MOSFET.[6][7] In 2003, NEC's research team led by Hitoshi Wakabayashi and Shigeharu Yamagami fabricated a 5 nm MOSFET.[8][9]

In July 2015, IBM announced that they had built the first functional transistors with 7 nm technology, using a silicon-germanium process.[10][11][12][13]

In June 2016, TSMC had produced 256 Mbit SRAM memory cells at their 7 nm process,[1] with a cell area of 0.027 um2 (550 F2) with reasonable risk production yields.[14]

Expected commercialization and technologies

In April 2016, TSMC announced that 7 nm trial production would begin in the first half of 2017.[15] In April 2017, TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm (N7FF+) process,[1] with extreme ultraviolet lithography (EUV).[16] TSMC's 7 nm production plans, as of early 2017, were to use deep ultraviolet (DUV) immersion lithography initially on this process node (N7FF), and transition from risk to commercial volume manufacturing from Q2 2017 to Q2 2018. Also, their later generation 7 nm (N7FF+) production is planned to use EUV multiple patterning and to have an estimated transition from risk to volume manufacturing between 2018 and 2019.[17]

In September 2016, GlobalFoundries announced trial production in the second half of 2017 and risk production in early 2018, with test chips already running.[18]

In February 2017, Intel announced Fab 42 in Chandler, Arizona will produce microprocessors using 7 nm manufacturing process.[19] The company has not published any expected values for feature lengths at this process node.

In April 2018, TSMC announced volume production of 7 nm (CLN7FF, N7) chips. In June 2018, the company announced mass production ramp up.[2]

In May 2018, Samsung announced production of 7 nm chips this year. ASML Holding NV is their main supplier of EUV lithography machines.[20]

In August 2018, GlobalFoundries announced it was stopping development of 7 nm chips, citing cost.[21]

On October 28, 2018, Samsung announced their second generation 7 nm process (7LPP) had entered risk production and should enter mass production in 2019.

On January 17, 2019, for the Q4 2018 earnings call, TSMC mentioned that different customers will have "different flavors" of second generation 7 nm.[22]

On April 16, 2019, TSMC announced their 6 nm process called (CLN6FF, N6), which is expected to be in mass products from 2021.[23] N6 uses EUVL in up to 5 layers, compared to up to 4 layers in their N7+ process.[24]

On July 28, 2019, TSMC announced their second gen 7 nm process called N7P, which is DUV-based like their N7 process.[25] Since N7P is fully IP-compatible with the original 7 nm, while N7+ (which uses EUV) is not, N7+ (announced earlier as '7 nm+') is a separate process from '7 nm'. N6 ('6 nm'), another EUV-based process, is planned to be released later than even TSMC's 5 nm (N5) process, with the IP-compatibility with N7. At their Q1 2019 earnings call, TSMC reiterated their Q4 2018 statement[22] that N7+ would generate less than $1 billion TWD in revenue in 2019.[26]

On October 5, 2019, AMD announced their EPYC Roadmap, featuring Milan chips built using TSMC's N7+ process.[27]

On October 7, 2019, TSMC announced they started delivering N7+ products to market in high volume.[28]

Technology commercialization

In June 2018, AMD announced 7 nm Radeon Instinct GPUs launching in the second half of 2018.[29] In August 2018, the company confirmed the release of the GPUs.[30]

On August 21, 2018, Huawei announced their HiSilicon Kirin 980 SoC to be used in their Huawei Mate 20 and Mate 20 Pro built using TSMC's 7 nm (N7) process.

On September 12, 2018, Apple announced their A12 Bionic chip used in iPhone XS and iPhone XR built using TSMC's 7 nm (N7) process. The A12 processor became the first 7 nm chip for mass market use as it released before the Huawei Mate 20.[31][32] In October 30, 2018, Apple announced their A12X Bionic chip used in iPad Pro built using TSMC's 7 nm (N7) process.[33]

On December 4, 2018, Qualcomm announced their Snapdragon 855 and 8cx built using TSMC's 7 nm (N7) process.[34] The first mass product featuring the Snapdragon 855 was the Lenovo Z5 Pro GT, which was announced on December 18, 2018.[35]

On May 29, 2019, MediaTek announced their 5G SoC built using a TSMC 7 nm process.[36]

On July 7, 2019, AMD officially launched their Ryzen 3000 series of central processing units, based on the TSMC 7 nm process and Zen 2 microarchitecture.

On August 6, 2019, Samsung announced their Exynos 9825 SoC, the first chip built using their 7LPP process. The Exynos 9825 is the first mass market chip built featuring EUVL.[37]

On September 6, 2019, Huawei announced their HiSilicon Kirin 990 4G & 990 5G SoCs, built using TSMC's N7 and N7+ processes.[38]

On September 10, 2019, Apple announced their A13 Bionic chip used in iPhone 11 and iPhone 11 Pro built using TSMC's 2nd gen N7P process.[39]

7 nm manufacturing made up 36% of TSMC's revenue in the second quarter of 2020.[40]

On August 17, 2020, IBM announced their IBM Power 10 processor.[39]

7 nm patterning difficulties
Pitch splitting issues. Successive litho-etch patterning is subject to overlay errors as well as the CD errors from different exposures.
Spacer patterning issues. Spacer patterning has excellent CD control for features directly patterned by the spacer, but the spaces between spacers may be split into core and gap populations.
Overlay error impact on line cut. An overlay error on a cut hole exposure could distort the line ends (top) or infringe on an adjacent line (bottom).
Two-bar EUV patterning issues. In EUV lithography, a pair of features may not have both features in focus at the same time; one will have different size from the other, and both will shift differently through focus as well.
7nm EUV stochastic failure probability. 7nm features are expected to approach ~20 nm width. The probability of EUV stochastic failure is measurably high for the commonly applied dose of 30 mJ/cm2.

The 7 nm foundry node is expected to utilize any of or a combination of the following patterning technologies: pitch splitting, self-aligned patterning, and EUV lithography. Each of these technologies carries significant challenges in critical dimension (CD) control as well as pattern placement, all involving neighboring features.

Pitch splitting

Pitch splitting involves splitting features that are too close together onto different masks, which are exposed successively, followed by litho-etch processing. Due to the use of different exposures, there is always the risk of overlay error between the two exposures, as well as different CDs resulting from the different exposures.

Spacer patterning

Spacer patterning involves depositing a layer onto pre-patterned features, then etching back to form spacers on the sidewalls of those features, referred to as core features. After removing the core features, the spacers are used as an etch mask to define trenches in the underlying layer. While the spacer CD control is generally excellent, the trench CD may fall into one of two populations, due to the two possibilities of being located where a core feature was located or in the remaining gap. This is known as 'pitch walking'.[41] Generally pitch = core CD + gap CD + 2 * spacer CD, but this does not guarantee core CD = gap CD. For FEOL features like gate or active area isolation (e.g., fins), the trench CD is not as critical as the spacer-defined CD, in which case, spacer patterning is actually the preferred patterning approach.

When self-aligned quadruple patterning (SAQP) is used, there is a second spacer that is utilized, replacing the first one. In this case, the core CD is replaced by core CD - 2* 2nd spacer CD, and the gap CD is replaced by gap CD - 2 * 2nd spacer CD. Thus, some feature dimensions are strictly defined by the second spacer CD, while the remaining feature dimensions are defined by the core CD, core pitch, and first and second spacer CD's. The core CD and core pitch are defined by conventional lithography, while the spacer CDs are independent of lithography. This is actually expected to have less variation than pitch splitting, where an additional exposure defines its own CD, both directly and through overlay.

Spacer-defined lines also require cutting. The cut spots may shift at exposure, resulting in distorted line ends or intrusions into adjacent lines.

EUV lithography

Extreme ultraviolet lithography (also known as EUV or EUVL) is capable of resolving features below 20 nm in conventional lithography style. However, the 3D reflective nature of the EUV mask results in new anomalies in the imaging. One particular nuisance is the two-bar effect, where a pair of identical bar-shaped features do not focus identically. One feature is essentially in the 'shadow' of the other. Consequently, the two features generally have different CDs which change through focus, and these features also shift position through focus.[42][43][44] This effect may be similar to what may be encountered with pitch splitting. A related issue is the difference of best focus among features of different pitches.[45]

EUV also has issues with reliably printing all features in a large population; some contacts may be completely missing or lines bridged. These are known as stochastic printing failures.[46][47] The defect level is on the order of 1K/mm2.[48]

The tip-to-tip gap is hard to control for EUV, largely due to the illumination constraint.[49] A separate exposure(s) for cutting lines is preferred.

Attenuated phase shift masks have been used in production for 90 nm node for adequate focus windows for arbitrarily pitched contacts with the ArF laser wavelength (193 nm),[50][51] whereas this resolution enhancement is not available for EUV.[52][53]

Comparison with previous nodes

Due to these challenges, 7 nm poses unprecedented patterning difficulty in the back end of line (BEOL). The previous high-volume, long-lived foundry node (Samsung 10 nm, TSMC 16 nm) used pitch splitting for the tighter pitch metal layers.[54][55][56]

Cycle time: immersion vs. EUV
Process Immersion (≥ 275 WPH)[57] EUV (1500 wafers/day)[58]
Single-patterned layer:
1 day completion by immersion		 6000 wafers/day 1500 wafers/day
Double-patterned layer:
2 days completion by immersion		 6000 wafers/2 days 3000 wafers/2 days
Triple-patterned layer:
3 days completion by immersion		 6000 wafers/3 days 4500 wafers/3 days
Quad-patterned layer:
4 days completion by immersion		 6000 wafers/4 days 6000 wafers/4 days

Due to the immersion tools being faster presently, multipatterning is still used on most layers. On the layers requiring immersion quad-patterning, the layer completion throughput by EUV is comparable. On the other layers, immersion would be more productive at completing the layer even with multipatterning.

7 nm process nodes and process offerings

The naming of process nodes by different major manufacturers (TSMC, Intel, Samsung, GlobalFoundries) is partially marketing-driven and not directly related to any measurable distance on a chip – for example TSMC's 7 nm node is similar in some key dimensions to Intel's 10 nm node (see transistor density, gate pitch and metal pitch in the following table). Nevertheless, as of 2017, the technological race to the greatest density was still competitive between the main players, with TSMC, Samsung, and Intel all holding leading positions between the years 2016 and 2017 when measured by the smallest feature size on chip.[59][60]

Since EUV implementation at 7 nm is still limited, multipatterning still plays an important part in cost and yield; EUV adds extra considerations. The resolution for most critical layers is still determined by multiple patterning. For example, for Samsung's 7 nm, even with EUV single-patterned 36 nm pitch layers, 44 nm pitch layers would still be quadruple patterned.[61]

TSMC N7FF[62] Samsung 7LPP[63][64] Intel 10 nm TSMC N7P ('2nd generation 7 nm')[25] TSMC N7FF+[65] TSMC N6
Transistor density (MTr/mm2) 96.5[66] 95.3 (7LPE)[67]
81.07 (57PP)
85.57 (54PP)[68]
100.76[69] same as N7FF 113.9[66] 114.2[23]
SRAM bit-cell size 0.027 μm2[70] 0.0262 μm2[70] 0.0312 μm2 same as N7FF Un­known Un­known
Transistor Gate Pitch 54 nm 54 nm 54 nm same as N7FF Un­known Un­known
Transistor Fin Pitch Un­known 27 nm 34 nm same as N7FF Un­known Un­known
Transistor Fin Height Un­known Un­known 53 nm Un­known Un­known Un­known
Minimum (metal) pitch 40 nm 46 nm 36 nm same as N7FF < 40 nm Un­known
EUV implementation None, used self-aligned quad patterning (SAQP) instead 36 nm pitch metal;[61]
20% of total layer set		 None. Relied on SAQP heavily None 4 layers 5 layers
EUV-limited wafer output N/A 1500 wafers/day[58] N/A N/A ~ 1000 wafers/day[71] Un­known
Multipatterning
(≥ 2 masks on a layer)		 Fins
Gate
Contacts/vias (quad-patterned)[72]
Lowest 10 metal layers		 Fins
Gate
Vias (double-patterned)[73]
Metal 1 (triple-patterned)[73]
44 nm pitch metal (quad-patterned)[61]		 Same as 7FF Same as 7FF, with reduction on 4 EUV layers Same as 7FF, with reduction on 5 EUV layers
Release status 2017 risk production
2018 production[1]		 2018 production 2019 production[74] 2019 production 2018 risk production[1]
2019 production		 2020 production

GlobalFoundries' 7 nm 7LP (Leading Performance) process would have offered 40% higher performance or 60%+ lower power with a 2x scaling in density and at a 30-45+% lower cost per die over its 14 nm process. The Contacted Poly Pitch (CPP) would have been 56 nm and the Minimum Metal Pitch (MMP) would have been 40 nm, produced with Self-Aligned Double Patterning (SADP). A 6T SRAM cell would have been 0.269 square microns in size. GlobalFoundries planned to eventually use EUV lithography in an improved process called 7LP+.[75] GlobalFoundries later stopped all 7 nm and beyond process development.

Intel has not revealed details about its 7 nm process, but its transistor density has been estimated to be around 202-250 million transistors per square millimeter.[76] As of 2020, Intel is experiencing problems with its 7 nm process to the point of outsourcing production of its Ponte Vecchio GPUs.[77][78] Intel's process has faced repeated delays, with mass production now expected in 2023.[79]

7 nm design rule management in volume production

The 7 nm metal patterning currently practiced by TSMC involves self-aligned double patterning (SADP) lines with cuts inserted within a cell on a separate mask as needed to reduce cell height.[80] However, self-aligned quad patterning (SAQP) is used to form the fin, the most important factor to performance.[81] Design rule checks also allow via multi-patterning to be avoided, and provide enough clearances for cuts that only one cut mask is needed.[81]

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Preceded by
10 nm		 MOSFET semiconductor device fabrication process Succeeded by
5 nm
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