Socket FM1

Socket FM1 is a CPU socket for desktop computers used by AMD early A-series APUs ("Llano") processors and Llano-derived Athlon II processors. It was released in July 2011. Its direct successors are Socket FM2 (September 2012) and Socket FM2+ (January 2014), while Socket AM1 (January 2014) is targeting low-power SoCs.

Socket FM1
TypePGA-ZIF
Chip form factorsPGA
Contacts905
FSB protocolUnified Media Interface (UMI)
FSB frequency100 MHz System clock
UMI up to 5,2 GT/s
Processorsearly A-series APUs
SuccessorFM2
This article is part of the CPU socket series

Chipsets

For available chipsets consult Fusion controller hubs (FCH).

Available APUs

APU's using Socket FM1 are AMD's Lynx platform.

Please consult List of AMD accelerated processing units for concrete product denominations.

Feature overview for AMD APUs

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

CodenameServer Basic Toronto
Micro Kyoto
Desktop Performance Renoir
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso
Entry
Basic Kabini
MobilePerformance Renoir Cezanne
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
Entry Dalí
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon		 Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family		 Prairie Falcon Banded Kestrel
Platform High, standard and low power Low and ultra-low power
ReleasedAug 2011Oct 2012Jun 2013Jan 2014 2015Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020 Jan 2021Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[1] Zen Zen+ Zen 2 Zen 3 Bobcat Jaguar Puma Puma+[2] "Excavator+" Zen
ISAx86-64x86-64
Socket Desktop High-end N/A
Mainstream N/A FM2+[lower-alpha 1] AM4
Entry FM1 FM2 FM2+[lower-alpha 2] AM1
Basic N/A N/A
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FT1 FT3 FT3b FP4 FP5
PCI Express version 2.0 3.0 4.0 2.0 3.0
Fab. (nm) GF 32SHP
(HKMG SOI)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)		 GF 12LP
(FinFET bulk)		 TSMC N7
(FinFET bulk)		 TSMC N40
(bulk)		 TSMC N28
(HKMG bulk)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)
Die area (mm2)228246245245250210[3]156 ?75 (+ 28 FCH)107?125149
Min TDP (W)351712104.543.95106
Max APU TDP (W)10095651825
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.8 ?1.752.222.23.23.3
Max APUs per node[lower-alpha 3]11
Max CPU[lower-alpha 4] cores per APU48242
Max threads per CPU core1212
Integer structure3+32+24+24+2+1 ?1+1+1+12+24+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU[lower-alpha 5]N/A
BMI1, AES-NI, CLMUL, and F16C N/A
MOVBEN/A
AVIC, BMI2 and RDRAND N/A
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERON/A N/A
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMITN/A N/A
FPUs per core10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit
CPU instruction set SIMD levelSSE4a[lower-alpha 6]AVX AVX2SSSE3AVXAVX2
3DNow!3DNow!+N/A N/A
PREFETCH/PREFETCHW
FMA4, LWP, TBM, and XOPN/AN/A N/AN/A
FMA3
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core10.51 10.51
Max APU total L1 instruction cache (KiB)256128192256512 6412896128
L1 instruction cache associativity (ways)2348 234
L2 caches per core10.5110.51
Max APU total L2 cache (MiB)424121
L2 cache associativity (ways)168168
APU total L3 cache (MiB)N/A48 N/A4
APU L3 cache associativity (ways)1616
L3 cache schemeVictimN/AVictimVictim
Max stock DRAM supportDDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266 LPDDR4-4266DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400
Max DRAM channels per APU2 12
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256 ?10.66612.80014.93319.20038.400
GPU microarchitectureTeraScale 2 (VLIW5)TeraScale 3 (VLIW4)GCN 2nd genGCN 3rd genGCN 5th gen[4]TeraScale 2 (VLIW5)GCN 2nd genGCN 3rd gen[4]GCN 5th gen
GPU instruction setTeraScale instruction setGCN instruction setTeraScale instruction setGCN instruction set
Max stock GPU base clock (MHz)6008008448661108125014002100 ?538600?8479001200
Max stock GPU base GFLOPS[lower-alpha 7]480614.4648.1886.71134.517601971.22150.4 ?86???345.6460.8
3D engine[lower-alpha 8]Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16[5]Up to 512:32:8 ?80:8:4128:8:4Up to 192:?:?Up to 192:?:?
IOMMUv1IOMMUv2 IOMMUv1?IOMMUv2
Video decoderUVD 3.0UVD 4.2UVD 6.0VCN 1.0[6]VCN 2.0[7]UVD 3.0UVD 4.0UVD 4.2UVD 6.0UVD 6.3VCN 1.0
Video encoderN/AVCE 1.0VCE 2.0VCE 3.1N/AVCE 2.0VCE 3.1
AMD Fluid Motion
GPU power savingPowerPlayPowerTunePowerPlayPowerTune[8]
TrueAudioN/A[9] N/A
FreeSync1
2		 1
2
HDCP[lower-alpha 9]?1.41.4
2.2		?1.41.4
2.2
PlayReady[lower-alpha 9]N/A3.0 not yetN/A3.0 not yet
Supported displays[lower-alpha 10]2–32–433 (desktop)
4 (mobile, embedded)		4234
/drm/radeon[lower-alpha 11][11][12]N/A N/A
/drm/amdgpu[lower-alpha 11][13]N/A[14] N/A[14]
  1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  3. A PC would be one node.
  4. An APU combines a CPU and a GPU. Both have cores.
  5. Requires firmware support.
  6. No SSE4. No SSSE3.
  7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. Unified shaders : texture mapping units : render output units
  9. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. To feed more than two displays, the additional panels must have native DisplayPort support.[10] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

See also

References
  1. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  2. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  3. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  4. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  5. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  6. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  7. Liu, Leo (2020-09-04). "Add Renoir VCN decode support". Retrieved 2020-09-11. It has same VCN2.x block as Navi1x
  8. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  9. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  10. "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  11. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  12. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  13. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  14. Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
This article is issued from Wikipedia. The text is licensed under Creative Commons - Attribution - Sharealike. Additional terms may apply for the media files.