Excavator (microarchitecture)

AMD Excavator Family 15h is a microarchitecture developed by AMD to succeed Steamroller Family 15h for use in AMD APU processors and normal CPUs. On October 12, 2011, AMD revealed Excavator to be the code name for the fourth-generation Bulldozer-derived core.

Excavator – Family 15h (4th-gen)
General information
Launched2015
Common manufacturer(s)
Architecture and classification
Min. feature size28 nm bulk silicon (GF28A)[1]
Instruction setAMD64 (x86-64)
Physical specifications
Socket(s)
Products, models, variants
Core name(s)
  • Carrizo
  • Bristol Ridge
  • Stoney Ridge
History
PredecessorSteamroller – Family 15h (3rd-gen)
SuccessorZen

The Excavator-based APU for mainstream applications is called Carrizo and was released in 2015.[2][3] The Carrizo APU is designed to be HSA 1.0 compliant.[4] An Excavator-based APU and CPU variant named Toronto for server and enterprise markets was also produced.[5]

Excavator was the final revision of the "Bulldozer" family, with two new microarchitectures replacing Excavator a year later.[6][7] Excavator was succeeded by the x86-64 Zen architecture in early 2017.[8][9]

Architecture

Excavator added hardware support for new instructions such as AVX2, BMI2 and RDRAND.[10] Excavator is designed using High Density (aka "Thin") Libraries normally used for GPUs to reduce electric energy consumption and die size, delivering a 30 percent increase in efficient energy use.[11] Excavator can process up to 15% more instructions per clock compared to AMD's previous core Steamroller.[12]

Features and ASICs

The following table shows features of AMD's APUs (see also: List of AMD accelerated processing units).

CodenameServer Basic Toronto
Micro Kyoto
Desktop Performance Renoir
Mainstream Llano Trinity Richland Kaveri Kaveri Refresh (Godavari) Carrizo Bristol Ridge Raven Ridge Picasso
Entry
Basic Kabini
MobilePerformance Renoir Cezanne
Mainstream Llano Trinity Richland Kaveri Carrizo Bristol Ridge Raven Ridge Picasso
Entry Dalí
Basic Desna, Ontario, Zacate Kabini, Temash Beema, Mullins Carrizo-L Stoney Ridge
Embedded Trinity Bald Eagle Merlin Falcon,
Brown Falcon		 Great Horned Owl Grey Hawk Ontario, Zacate Kabini Steppe Eagle, Crowned Eagle,
LX-Family		 Prairie Falcon Banded Kestrel
Platform High, standard and low power Low and ultra-low power
ReleasedAug 2011Oct 2012Jun 2013Jan 2014 2015Jun 2015Jun 2016Oct 2017Jan 2019Mar 2020 Jan 2021Jan 2011May 2013Apr 2014May 2015Feb 2016Apr 2019
CPU microarchitecture K10 Piledriver Steamroller Excavator "Excavator+"[13] Zen Zen+ Zen 2 Zen 3 Bobcat Jaguar Puma Puma+[14] "Excavator+" Zen
ISAx86-64x86-64
Socket Desktop High-end N/A
Mainstream N/A FM2+[lower-alpha 1] AM4
Entry FM1 FM2 FM2+[lower-alpha 2] AM1
Basic N/A N/A
Other FS1 FS1+, FP2 FP3 FP4 FP5 FP6 FT1 FT3 FT3b FP4 FP5
PCI Express version 2.0 3.0 4.0 2.0 3.0
Fab. (nm) GF 32SHP
(HKMG SOI)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)		 GF 12LP
(FinFET bulk)		 TSMC N7
(FinFET bulk)		 TSMC N40
(bulk)		 TSMC N28
(HKMG bulk)		 GF 28SHP
(HKMG bulk)		 GF 14LPP
(FinFET bulk)
Die area (mm2)228246245245250210[15]156 ?75 (+ 28 FCH)107?125149
Min TDP (W)351712104.543.95106
Max APU TDP (W)10095651825
Max stock APU base clock (GHz)33.84.14.13.73.83.63.73.8 ?1.752.222.23.23.3
Max APUs per node[lower-alpha 3]11
Max CPU[lower-alpha 4] cores per APU48242
Max threads per CPU core1212
Integer structure3+32+24+24+2+1 ?1+1+1+12+24+2
i386, i486, i586, CMOV, NOPL, i686, PAE, NX bit, CMPXCHG16B, AMD-V, RVI, ABM, and 64-bit LAHF/SAHF
IOMMU[lower-alpha 5]N/A
BMI1, AES-NI, CLMUL, and F16C N/A
MOVBEN/A
AVIC, BMI2 and RDRAND N/A
ADX, SHA, RDSEED, SMAP, SMEP, XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, and CLZERON/A N/A
WBNOINVD, CLWB, RDPID, RDPRU, and MCOMMITN/A N/A
FPUs per core10.5110.51
Pipes per FPU22
FPU pipe width128-bit256-bit80-bit128-bit
CPU instruction set SIMD levelSSE4a[lower-alpha 6]AVX AVX2SSSE3AVXAVX2
3DNow!3DNow!+N/A N/A
PREFETCH/PREFETCHW
FMA4, LWP, TBM, and XOPN/AN/A N/AN/A
FMA3
L1 data cache per core (KiB)64163232
L1 data cache associativity (ways)2488
L1 instruction caches per core10.51 10.51
Max APU total L1 instruction cache (KiB)256128192256512 6412896128
L1 instruction cache associativity (ways)2348 234
L2 caches per core10.5110.51
Max APU total L2 cache (MiB)424121
L2 cache associativity (ways)168168
APU total L3 cache (MiB)N/A48 N/A4
APU L3 cache associativity (ways)1616
L3 cache schemeVictimN/AVictimVictim
Max stock DRAM supportDDR3-1866DDR3-2133DDR3-2133, DDR4-2400DDR4-2400DDR4-2933DDR4-3200, LPDDR4-4266 LPDDR4-4266DDR3L-1333DDR3L-1600DDR3L-1866DDR3-1866, DDR4-2400DDR4-2400
Max DRAM channels per APU2 12
Max stock DRAM bandwidth (GB/s) per APU29.86634.13238.40046.93268.256 ?10.66612.80014.93319.20038.400
GPU microarchitectureTeraScale 2 (VLIW5)TeraScale 3 (VLIW4)GCN 2nd genGCN 3rd genGCN 5th gen[16]TeraScale 2 (VLIW5)GCN 2nd genGCN 3rd gen[16]GCN 5th gen
GPU instruction setTeraScale instruction setGCN instruction setTeraScale instruction setGCN instruction set
Max stock GPU base clock (MHz)6008008448661108125014002100 ?538600?8479001200
Max stock GPU base GFLOPS[lower-alpha 7]480614.4648.1886.71134.517601971.22150.4 ?86???345.6460.8
3D engine[lower-alpha 8]Up to 400:20:8Up to 384:24:6Up to 512:32:8Up to 704:44:16[17]Up to 512:32:8 ?80:8:4128:8:4Up to 192:?:?Up to 192:?:?
IOMMUv1IOMMUv2 IOMMUv1?IOMMUv2
Video decoderUVD 3.0UVD 4.2UVD 6.0VCN 1.0[18]VCN 2.0[19]UVD 3.0UVD 4.0UVD 4.2UVD 6.0UVD 6.3VCN 1.0
Video encoderN/AVCE 1.0VCE 2.0VCE 3.1N/AVCE 2.0VCE 3.1
AMD Fluid Motion
GPU power savingPowerPlayPowerTunePowerPlayPowerTune[20]
TrueAudioN/A[21] N/A
FreeSync1
2		 1
2
HDCP[lower-alpha 9]?1.41.4
2.2		?1.41.4
2.2
PlayReady[lower-alpha 9]N/A3.0 not yetN/A3.0 not yet
Supported displays[lower-alpha 10]2–32–433 (desktop)
4 (mobile, embedded)		4234
/drm/radeon[lower-alpha 11][23][24]N/A N/A
/drm/amdgpu[lower-alpha 11][25]N/A[26] N/A[26]
  1. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  2. For FM2+ Excavator models: A8-7680, A6-7480 & Athlon X4 845.
  3. A PC would be one node.
  4. An APU combines a CPU and a GPU. Both have cores.
  5. Requires firmware support.
  6. No SSE4. No SSSE3.
  7. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.
  8. Unified shaders : texture mapping units : render output units
  9. To play protected video content, it also requires card, operating system, driver, and application support. A compatible HDCP display is also needed for this. HDCP is mandatory for the output of certain audio formats, placing additional constraints on the multimedia setup.
  10. To feed more than two displays, the additional panels must have native DisplayPort support.[22] Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.
  11. DRM (Direct Rendering Manager) is a component of the Linux kernel. Support in this table refers to the most current version.

Processors

APU lines

There are three APU lines announced or released:

  1. Budget and mainstream markets (desktop and mobile): Carrizo APU
    • The Carrizo mobile APUs were launched in 2015 based on Excavator x86 cores and featuring Heterogeneous System Architecture for integrated task sharing between CPUs and GPUs, which allows a GPU to perform compute functions, which is claimed provide greater performance increases than shrinking the feature size alone.[4]
    • Carrizo desktop APUs were launched in 2018. The mainstream product (A8-7680) has 4 Excavator cores and a GPU based on GCN1.2 architecture. Also, an entry-level APU (A6-7480) with 2 Excavator cores is also launched.
  2. Budget and mainstream markets (desktop and mobile): Bristol Ridge, and Stoney Ridge (for entry level notebooks), APUs[27]
    • Bristol Ridge APUs utilize socket AM4 and DDR4 RAM
    • Bristol Ridge APUs have up to 4 Excavator CPU cores and up to 8 3rd generation GCN GPU cores
    • Up to a 20% CPU performance increase over Carrizo
    • TDP of 15W to 65W, 15–35W for mobile
  3. Enterprise and server markets: Toronto APU
    • The Toronto APU for server and enterprise markets featured four x86 Excavator CPU core modules and Volcanic Islands integrated GPU core.
    • The Excavator cores has a greater advantage with IPC than Steamroller. The improvement is 4–15%.
    • Support for HSA/hUMA, DDR3/DDR4, PCIe 3.0, GCN 1.2[4][5][9]
    • The Toronto APU was available in BGA and SoC variants. The SoC variant had the southbridge on the same die as the APU to save space and power and to optimize workloads.
    • A complete system with a Toronto APU would have a maximum power usage of 70 W.[5]

CPU Desktop lines

There are no plans for Steamroller (3rd gen Bulldozer) or Excavator (4th gen Bulldozer) architectures on high-end desktop platforms.

Excavator CPU for Desktop announced on 2nd Feb 2016, named Athlon X4 845.[28]In 2017, three more desktop CPUs (Athlon X4 9x0) were launched. They come in Socket AM4, with a TDP of 65W. In fact, they are APUs with their graphics cores disabled.

List of desktop Excavator CPUs
CPU modelFrequency (GHz)CoresTDP (Watt) SocketL1D cacheL2 cachePCI Express 3.0Relative IPC Locked
Athlon X4 845 (Carrizo)3.5 (3.8 turbo)465 Socket FM2+ (906)4*32KB2*1MBX81.0 Yes
Athlon X4 940 (Bristol Ridge)3.2 (3.6 turbo)465 Socket AM4 (1331)4*32KB2*1MBX161.1 No
Athlon X4 950 (Bristol Ridge) 3.5 (3.8 turbo) 4 65 Socket AM4 (1331) 4*32KB 2*1MB X16 1.1 No
Athlon X4 970 (Bristol Ridge) 3.8 (4.0 turbo) 4 65 Socket AM4 (1331) 4*32KB 2*1MB X16 1.1 No

Server lines
Main article: List of AMD Opteron microprocessors

The AMD Opteron roadmaps for 2015 show the Excavator-based Toronto APU and Toronto CPU intended for 1 Processor (1P) cluster applications:[5]

  • For 1P Web and Enterprise Services Clusters:
    • Toronto CPU – quad-core x86 Excavator architecture
    • plans for Cambridge CPU – 64-bit AArch64 core
  • For 1P Compute and Media Clusters:
    • Toronto APU – quad-core x86 Excavator architecture
  • For 2P/4P Servers:

References
  1. http://www.extremetech.com/computing/176919-amd-leak-confirms-that-excavator-apu-will-be-28nm-and-that-some-production-is-moving-back-to-globalfoundries
  2. Reynolds, Sam (October 31, 2013). "New confirmed details on AMD's 2014 APU lineup, Kaveri delayed". Vr-zone.com. Retrieved November 24, 2013.
  3. "AMD updates product roadmap for 2014 and 2015". Digitimes.com. August 26, 2013. Retrieved November 24, 2013.
  4. Hachman, Mark (November 21, 2014). "AMD reveals high-end 'Carrizo' APU, the first chip to fully embrace audacious HSA tech". PCWorld. Retrieved January 15, 2015.
  5. Mujtaba, Hassan (December 26, 2013). "AMD Opteron Roadmap Reveals Next Generation Toronto and Carrizo APU Details". WCCF Tech. Retrieved January 15, 2015.
  6. http://www.bit-tech.net/news/hardware/2014/09/11/amd-zen/1
  7. "Archived copy". Archived from the original on 2014-05-13. Retrieved 2014-05-22.CS1 maint: archived copy as title (link)
  8. Moammer, Khalid (September 9, 2014). "AMD's Next Gen x86 High Performance Core is Zen". WCCF Tech. Retrieved January 15, 2015.
  9. Mujtaba, Hassan (May 5, 2014). "AMD Announces 2014-2016 Roadmap – 20nm Project SkyBridge and K12 64-bit ARM Cores For 2016". WCCF Tech. Retrieved January 15, 2015.
  10. "AMDs Carrizo architecture detailed and explored". Extremetech.com. June 2, 2015. Retrieved March 3, 2019.
  11. http://www.tomshardware.com/news/Steamroller-High_Density_Libraries-hot-chips-cpu-gpu,17218.html
  12. http://wccftech.com/amd-carrizo-apu-architecture-hot-chips/
  13. "AMD Announces the 7th Generation APU: Excavator mk2 in Bristol Ridge and Stoney Ridge for Notebooks". 31 May 2016. Retrieved 3 January 2020.
  14. "AMD Mobile "Carrizo" Family of APUs Designed to Deliver Significant Leap in Performance, Energy Efficiency in 2015" (Press release). 20 November 2014. Retrieved 16 February 2015.
  15. "The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List". TechARP.com. Retrieved 13 December 2017.
  16. "AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver". VideoCardz.com. Retrieved 6 June 2017.
  17. Cutress, Ian (1 February 2018). "Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm". Anandtech. Retrieved 7 February 2018.
  18. Larabel, Michael (17 November 2017). "Radeon VCN Encode Support Lands in Mesa 17.4 Git". Phoronix. Retrieved 20 November 2017.
  19. Liu, Leo (2020-09-04). "Add Renoir VCN decode support". Retrieved 2020-09-11. It has same VCN2.x block as Navi1x
  20. Tony Chen; Jason Greaves, "AMD's Graphics Core Next (GCN) Architecture" (PDF), AMD, retrieved 13 August 2016
  21. "A technical look at AMD's Kaveri architecture". Semi Accurate. Retrieved 6 July 2014.
  22. "How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card?". AMD. Retrieved 8 December 2014.
  23. Airlie, David (26 November 2009). "DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33". Retrieved 16 January 2016.
  24. "Radeon feature matrix". freedesktop.org. Retrieved 10 January 2016.
  25. Deucher, Alexander (16 September 2015). "XDC2015: AMDGPU" (PDF). Retrieved 16 January 2016.
  26. Michel Dänzer (17 November 2016). "[ANNOUNCE] xf86-video-amdgpu 1.2.0". lists.x.org.
  27. Cutress, Ian (1 June 2016). "AMD Announces 7th Generation APU". Anandtech.com. Retrieved 1 June 2016.
  28. Jeff Kampman (2 February 2016). "AMD puts Excavator on the desktop with the Athlon X4 845".
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