Zen 3

Zen 3 is a significant incremental improvement over its predecessors, with an IPC increase of 19%,[8] and being capable of reaching higher clock speeds.

Like Zen 2, Zen 3 is composed of up to 2 core complex dies (CCD) along with a separate IO die containing the I/O components. A Zen 3 CCD is composed of a single core complex (CCX) containing 8 CPU cores and 32 MB of shared L3 cache, this is in contrast to Zen 2 where each CCD is composed of 2 CCX, each containing 4 cores each as well as 16 MB of L3 cache. The new configuration allows all 8 cores of the CCX to directly communicate with each other and the L3 Cache instead of having to use the IO die through the Infinity Fabric.[8]

Zen 3 also features Smart Access Memory (SAM), a technology allowing Zen 3 processors to directly access all of a compatible graphic card's VRAM,[9] allowing an increased FPS of up to 11% in certain games.[10] SAM is an implementation of resizable BAR, an optional feature introduced in PCIe 2.0 that, as of the launch of Zen 3, only AMD has explored.[11] As of December 2020, Intel and Nvidia are reportedly working on implementing Resizable BAR in the near future.

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  A delidded Ryzen 5 5600X. Only one CCD is present. The contacts for a second CCD are visible.
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  Close up of the CCD, taken under infrared lighting. The die broke during delidding.
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  Close up of the I/O Die

In Zen 3, a single 32MB L3 cache pool is shared among all 8 cores in a chiplet, vs Zen 2's two 16MB pools each shared among 4 cores in a core complex, of which there were two per chiplet. This new arrangement improves the cache hit rate as well as performance in situations that require cache data to be exchanged among cores, but increases cache latency from 39 cycles in Zen 2 to 46 clock cycles and halves per-core cache bandwidth, although both problems are partially mitigated by higher clock speeds. Total cache bandwidth on all 8 cores combined remains the same due to power consumption concerns. L2 cache capacity and latency remain the same at 512KB and 12 cycles. All cache read and write operations are done at 32 bytes per cycle.[2]

On October 8, 2020, AMD announced four Zen 3-based desktop Ryzen processors, consisting of one Ryzen 5, one Ryzen 7, and two Ryzen 9 CPUs and featuring between 6 and 16 cores.[1]