Espresso (microprocessor)

An illustration of the Wii U MCM with heat spreader. The markings indicate that it is designed by Nintendo, and its components are made by AMD, IBM and Renesas. It also says that it was assembled in Japan, the 26th week of 2012.

Wii U MCM without heat spreader.

IBM and Nintendo have revealed that the Espresso processor is a PowerPC-based microprocessor with three cores on a single chip to reduce power consumption and increase speed. The CPU and the graphics processor are placed on a single substrate as a multi-chip module (MCM) to reduce complexity, increase the communication speed between the chips, further reduce power consumption and reduce cost and space required. The two chips were assembled to the complete MCM by Renesas in Japan.[1] Espresso itself was manufactured by IBM in its 300 mm plant in East Fishkill, New York, using 45 nm SOI-technology[2] and embedded DRAM (eDRAM) for caches.

While unverified by Nintendo, hackers, teardowns, and unofficial informants have since revealed more information about the Espresso, such as its name,[3] size[4][5] and speed.[6][7] The microarchitecture seems to be quite similar to its predecessors the Broadway and Gekko, i.e. PowerPC 750 based, but enhanced with larger and faster caches and multiprocessor support.

Rumors that the Wii U CPU was derived from IBM's high-end POWER7 server processor proved false, as it would potentially increase the manufacturing and retail cost of the system, and require a larger form factor. Espresso shares some technology with POWER7, such as eDRAM and general instruction set similarities, but those are superficial similarities.[8][9][10][11][12]

• Out-of-order execution PowerPC based cores
• 45 nanometer process technology
• IBM silicon on insulator (SOI) technology
• Backward compatible with the Broadway and Gekko processors

The following specifications have not been officially confirmed by either Nintendo or IBM. They have been obtained by reverse engineering by hacker Hector Martin, who goes by the alias marcan.[13]

• Broadway-based core architecture[14]
• Three cores at 1.243125 GHz
• Symmetric multiprocessing with MESI/MERSI support[15]
• Each core can output up to 4 instructions per clock using superscalar parallelism.
• 32-bit integer unit
• 64-bit floating-point (or 2× 32-bit SIMD, often found under the denomination "paired singles")
• A total of 3 MB of Level 2 cache in an unusual configuration.[16]
  • Core 0: 512 KB, core 1: 2 MB, core 2: 512 KB
• 4 stage pipeline [17]
• 7 stage pipeline - FP[17]
• 6 Execution Units per core (18 EUs total)[17]
• Die size: 4.74 mm × 5.85 mm = 27.73 mm²

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