POWER10

Each POWER10 core has doubled up on most functional units compared to its predecessor POWER9. The core is eight-way multithreaded (SMT8) and has 48 kB instruction and 32 kB data L1 caches, a 2 MB large L2 cache and a very large translation lookaside buffer (TLB) with 4096 entries.[3] Latency cycles to the different cache stages and TLB has been reduced significantly. Each core has eight execution slices each with one floating-point unit (FPU), arithmetic logic unit (ALU), branch predictor, load–store unit and SIMD-engine, able to be fed 128-bit (64+64) instructions from the new prefix/fuse instructions of the Power ISA v.3.1. Each execution slice can handle 20 instructions each, backed up by a shared 512 entry instruction table, and fed to 128 entry wide (64 single threaded) load queue and 80 entry (40 single threaded) wide store queue. Better branch prediction features have doubled the accuracy. A core has four matrix math assist (MMA) engines, for better handling of SIMD code, especially for matrix multiplication instructions where AI inference workloads have a 20-fold performance increase.[6]

The whole processor have two "hemispheres" with eight cores, sharing a 64 MB L3 cache for a total of 16 cores and 128 MB L3 caches. Due to yield issues, at least one core is always disabled, reducing L3 cache by 8 MB to a usable total of 15 cores and 120 MB L3 cache. Each chip also has eight crypto accelerators offloading common algorithms such as AES and SHA-3.

Increased clock gating and reworked microarchitecture at every stage, together with the fuse/prefix instructions enabling more work with fewer work units, and smarter cache with lower memory latencies and effective address tagging reducing cache misses, enables the POWER10 core consume half the power as POWER9. Combined with the improvements in the compute facilities by up to 30% makes the whole processor perform 2.6× better per watt than its predecessor. And in the case of mounting two cores on the same module, up to 3 times as fast in the same power budget.

As the cores can act like eight logical processors the 15 core processor looks like 120 cores to the operating system. On a dual chip module, that becomes 240 simultaneous threads per socket.

• Linux, version 5.9[9]
• PowerVM with nested Kernel-based Virtual Machine (KVM)
• AIX[10]
• IBM i[10]

The change to a 7-nm fabrication process results in significantly be higher performance per watt.

The PowerAXON facility now extends all the way to 2 PB of unified clustered memory space, shared across multiple cluster nodes, and includes support for PCIe 5.

New SIMD instructions and new datatypes including bfloat16, INT4(INTEGER) and INT8(BIGINT).[11][12] are aimed at improving AI workloads.

• IBM POWER microprocessors
• OpenPOWER Foundation
• POWER9