Zen (first generation microarchitecture)

Zen is the codename for the first iteration in a family of computer processor microarchitectures of the same name from AMD. It was first used with their Ryzen series of CPUs in February 2017.[3] The first Zen-based preview system was demonstrated at E3 2016, and first substantially detailed at an event hosted a block away from the Intel Developer Forum 2016. The first Zen-based CPUs codenamed "Summit Ridge" reached the market in early March 2017, Zen-derived Epyc server processors launched in June 2017[10] and Zen-based APUs arrived in November 2017.[11]

AMD Zen
The logo for the Zen microarchitecture is a closed ensō
General information
LaunchedMarch 2, 2017 (March 2, 2017)[1]
Designed byAMD
Common manufacturer(s)
CPUID codeFamily 17h
Cache
L1 cache64 KiB instruction, 32 KiB data per core
L2 cache512 KiB per core
L3 cache8 MiB per quad-core CCX
Architecture and classification
Instruction setAMD64 (x86-64)
Physical specifications
Transistors
Cores
    • 2–4 (essential)
    • 4–8 (mainstream)
    • 8–16 (enthusiast)[3][4][5][6]
    • Up to 32 (server)[3][7]
Socket(s)
Products, models, variants
Product code name(s)
  • Summit Ridge (Desktop)
  • Whitehaven (HEDT)
  • Raven Ridge (APU/Embedded)
  • Naples (Server CPU)
  • Snowy Owl (Server APU)[9]
Brand name(s)
History
PredecessorExcavator (4th gen)
SuccessorZen+
This article is about the first generation of the Zen microarchitecture. For the CPU architecture family, see Zen (microarchitecture).

Zen is a clean sheet design that differs from AMD's previous long-standing Bulldozer architecture. Zen-based processors use a 14 nm FinFET process, are reportedly more energy efficient, and can execute significantly more instructions per cycle. SMT has been introduced, allowing each core to run two threads. The cache system has also been redesigned, making the L1 cache write-back. Zen processors use three different sockets: desktop and mobile Ryzen chips use the AM4 socket, bringing DDR4 support; the high-end desktop Zen-based Threadripper chips support quad-channel DDR4 RAM and offer 64 PCIe 3.0 lanes (vs 24 lanes), using the TR4 socket;[12][13] and Epyc server processors offer 128 PCI 3.0 lanes and octa-channel DDR4 using the SP3 socket.

Zen is based on a SoC design.[14] The memory, PCIe, SATA, and USB controllers are incorporated into the same chip(s) as the processor cores. This has advantages in bandwidth and power, at the expense of chip complexity and die area.[15] This SoC design allows the Zen microarchitecture to scale from laptops and small-form factor mini PCs to high-end desktops and servers.

By 2020, 260 million Zen cores have already been shipped by AMD.[16]

Design
A highly simplified illustration of the Zen microarchitecture: a core has a total of 512 KiB of L2 cache.
Ryzen 3 1200 Die Shot
Photomontage of an delidded Zen CPU with an etched die.
A delidded AMD EPYC processor used in servers; The four dies are similar to the ones used in mainstream processors. All EPYC processors contain four dies to provide structural support to the IHS (Integrated Heat Spreader).[17][18][19]
A delidded AMD Athlon 3000G APU, based on the Zen architecture. The die is physically smaller than those on mainstream Zen processors.
Die shot of an AMD Athlon 3000G

According to AMD, the main focus of Zen is on increasing per-core performance.[20][21][22] New or improved features include:[23]

  • The L1 cache has been changed from write-through to write-back, allowing for lower latency and higher bandwidth.
  • SMT (simultaneous multithreading) architecture allows for two threads per core, a departure from the CMT (clustered multi-thread) design used in the previous Bulldozer architecture. This is a feature previously offered in some IBM, Intel and Oracle processors.[24]
  • A fundamental building block for all Zen-based CPUs is the Core Complex (CCX) consisting of four cores and their associated caches. Processors with more than four cores consist of multiple CCXs connected by Infinity Fabric.[25] Processors with non-multiple-of-four core counts have some cores disabled.
  • Four ALUs, two AGUs/load–store units, and two floating-point units per core.[26]
  • Newly introduced "large" micro-operation cache.[27]
  • Each SMT core can dispatch up to six micro-ops per cycle (a combination of 6 integer micro-ops and 4 floating point micro-ops per cycle).[28][29]
  • Close to 2× faster L1 and L2 bandwidth, with total L3 cache bandwidth up 5×.
  • Clock gating.
  • Larger retire, load, and store queues.
  • Improved branch prediction using a hashed perceptron system with Indirect Target Array similar to the Bobcat microarchitecture,[30] something that has been compared to a neural network by AMD engineer Mike Clark.[31]
  • The branch predictor is decoupled from the fetch stage.
  • A dedicated stack engine for modifying the stack pointer, similar to that of Intel Haswell and Broadwell processors.[32]
  • Move elimination, a method that reduces physical data movement to reduce power consumption.
  • Binary compatibility with Intel's Skylake (excluding VT-x and private MSRs):
  • CLZERO instruction for clearing a cache line.[33] Useful for handling ECC-related Machine-check exceptions.
  • PTE (page table entry) coalescing, which combines 4 kiB page tables into 32 kiB page size.
  • "Pure Power" (more accurate power monitoring sensors).[34]
    • Support for intel-style running average power limit (RAPL) measurement.[35]
  • Smart Prefetch.
  • Precision Boost.
  • eXtended Frequency Range (XFR), an automated overclocking feature which boosts clock speeds beyond the advertised turbo frequency.[36]

This is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do. It is a multi-year project with a really large team. It's like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and power consumption over the previous generation.

— Suzanne Plummer, Zen team leader, on September 19th, 2015.[37]

The Zen architecture is built on a 14 nanometer FinFET process subcontracted to GlobalFoundries,[38] which in turn licenses its 14 nm process from Samsung Electronics.[39] This gives greater efficiency than the 32 nm and 28 nm processes of previous AMD FX CPUs and AMD APUs, respectively.[40] The "Summit Ridge" Zen family of CPUs use the AM4 socket and feature DDR4 support and a 95 W TDP (thermal design power).[40] While newer roadmaps don't confirm the TDP for desktop products, they suggest a range for low-power mobile products with up to two Zen cores from 5 to 15 W and 15 to 35 W for performance-oriented mobile products with up to four Zen cores.[41]

Each Zen core can decode four instructions per clock cycle and includes a micro-op cache which feeds two schedulers, one each for the integer and floating point segments.[42][43] Each core has two address generation units, four integer units, and four floating point units. Two of the floating point units are adders, and two are multiply-adders. However, using multiply-add-operations may prevent simultaneous add operation in one of the adder units.[44] There are also improvements in the branch predictor. The L1 cache size is 64 KiB for instructions per core and 32 KiB for data per core. The L2 cache size 512 KiB per core, and the L3 is 1–2 MB per core. L3 caches offer 5× the bandwidth of previous AMD designs.

History and development

AMD began planning the Zen microarchitecture shortly after re-hiring Jim Keller in August 2012.[45] AMD formally revealed Zen in 2015.

The team in charge of Zen was led by Keller (who left in September 2015 after a 3-year tenure) and Zen Team Leader Suzanne Plummer.[46][47] The Chief Architect of Zen was AMD Senior Fellow Michael Clark.[48][49][50]

Zen was originally planned for 2017 following the ARM64-based K12 sister core, but on AMD's 2015 Financial Analyst Day it was revealed that K12 was delayed in favor of the Zen design, to allow it to enter the market within the 2016 timeframe,[8] with the release of the first Zen-based processors expected for October 2016.[51]

In November 2015, a source inside AMD reported that Zen microprocessors had been tested and "met all expectations" with "no significant bottlenecks found".[2][52]

In December 2015, it was rumored that Samsung may have been contracted as a fabricator for AMD's 14 nm FinFET processors, including both Zen and AMD's then-upcoming Polaris GPU architecture.[53] This was clarified by AMD's July 2016 announcement that products had been successfully produced on Samsung's 14 nm FinFET process.[54] AMD stated Samsung would be used "if needed", arguing this would reduce risk for AMD by decreasing dependence on any one foundry.

In December 2019, AMD started putting out first generation Ryzen products built using the second generation Zen+ architecture.[55]

Advantages over predecessors

Manufacturing process

Processors based on Zen use 14 nm FinFET silicon.[56] These processors are reportedly produced at GlobalFoundries.[57] Prior to Zen, AMD's smallest process size was 28 nm, as utilized by their Steamroller and Excavator microarchitectures.[58][59] The immediate competition, Intel's Skylake and Kaby Lake microarchitecture, are also fabricated on 14 nm FinFET;[60] though Intel planned to begin the release of 10 nm parts later in 2017.[61] In comparison to Intel's 14 nm FinFET, AMD claimed in February 2017 the Zen cores would be 10% smaller.[62] Intel has later announced in July 2018 that 10nm mainstream processors should not be expected before the second half of 2019.[63]

For identical designs, these die shrinks would use less current (and power) at the same frequency (or voltage). As CPUs are usually power limited (typically up to ~125 W, or ~45 W for mobile), smaller transistors allow for either lower power at the same frequency, or higher frequency at the same power.[64]

Performance

One of Zen's major goals in 2016 was to focus on performance per-core, and it was targeting a 40% improvement in instructions per cycle (IPC) over its predecessor.[65] Excavator, in comparison, offered 4–15% improvement over previous architectures.[66][67] AMD announced the final Zen microarchitecture actually achieved 52% improvement in IPC over Excavator.[68] The inclusion of SMT also allows each core to process up to two threads, increasing processing throughput by better use of available resources.

The Zen processors also employ sensors across the chip to dynamically scale frequency and voltage.[69] This allows for the maximum frequency to be dynamically and automatically defined by the processor itself based upon available cooling.

AMD has demonstrated an 8-core/16-thread Zen processor outperforming an equally-clocked Intel Broadwell-E processor in Blender rendering[3][9] and HandBrake benchmarks.[69]

Zen supports AVX2 but it requires two clock cycles to complete each AVX2 instruction compared to Intel's one.[70][71] This difference was corrected in Zen 2.

Memory

Zen supports DDR4 memory (up to eight channels)[72] and ECC.[73]

Pre-release reports stated APUs using the Zen architecture would also support High Bandwidth Memory (HBM).[74] However, the first demonstrated APU did not use HBM.[75] Previous APUs from AMD relied on shared memory for both the GPU and the CPU.

Power consumption and heat output

Processors built at the 14 nm node on FinFET silicon should show reduced power consumption and therefore heat over their 28 nm and 32 nm non-FinFET predecessors (for equivalent designs), or be more computationally powerful at equivalent heat output/power consumption.

Zen also uses clock gating,[43] reducing the frequency of underutilized portions of the core to save power. This comes from AMD's SenseMI technology, using sensors across the chip to dynamically scale frequency and voltage.[69]

Enhanced security and virtualization support

Zen added support for AMD's Secure Memory Encryption (SME) and AMD's Secure Encrypted Virtualization (SEV). Secure Memory Encryption is real-time memory encryption done per page table entry. Encryption occurs on a hardware AES engine and keys are managed by the onboard "Security" Processor (ARM Cortex-A5) at boot time to encrypt each page, allowing any DDR4 memory (including non-volatile varieties) to be encrypted. AMD SME also makes the contents of the memory more resistant to memory snooping and cold boot attacks.[76][77]

SME can be used to mark individual pages of memory as encrypted through the page tables. A page of memory that is marked encrypted will be automatically decrypted when read from DRAM and will be automatically encrypted when written to DRAM. The SME feature is identified through a CPUID function and enabled through the SYSCFG MSR. Once enabled, page table entries will determine how the memory is accessed. If a page table entry has the memory encryption mask set, then that memory will be accessed as encrypted memory. The memory encryption mask (as well as other related information) is determined from settings returned through the same CPUID function that identifies the presence of the feature.

[78]

The Secure Encrypted Virtualization (SEV) feature allows the memory contents of a virtual machine (VM) to be transparently encrypted with a key unique to the guest VM. The memory controller contains a high-performance encryption engine which can be programmed with multiple keys for use by different VMs in the system. The programming and management of these keys is handled by the AMD Secure Processor firmware which exposes an API for these tasks.[79]

Connectivity

Incorporating much of the southbridge into the SoC, the Zen CPU includes SATA, USB, and PCI Express NVMe links.[80][81] This can be augmented by available Socket AM4 chipsets which add connectivity options including additional SATA and USB connections, and support for AMD's Crossfire and Nvidia's SLI.[82]

AMD, in announcing its Radeon Instinct line, argued that the upcoming Zen-based Naples server CPU would be particularly suited for building deep learning systems.[83][84] The 128[85] PCIe lanes per Naples CPU allows for eight Instinct cards to connect at PCIe x16 to a single CPU. This compares favorably to the Intel Xeon line, with only 40 PCIe lanes.

Features

CPUs

CPU features table

APUs

APU features table

Products

The Zen architecture is used in the current-generation desktop Ryzen CPUs. It is also in Epyc server processors (successor of Opteron processors), and APUs.[74][86][87]

The first desktop processors without graphics processing units (codenamed "Summit Ridge") were initially expected to start selling at the end of 2016, according to an AMD roadmap; with the first mobile and desktop processors of the AMD Accelerated Processing Unit type (codenamed "Raven Ridge") following in late 2017.[88] AMD officially delayed Zen until Q1 of 2017. In August 2016, an early demonstration of the architecture showed an 8-core/16-thread engineering sample CPU at 3.0 GHz.[9]

In December 2016, AMD officially announced the desktop CPU line under the Ryzen brand for release in Q1 2017. It also confirmed Server processors would be released in Q2 2017, and mobile APUs in H2 2017.[89]

On March 2, 2017, AMD officially launched the first Zen architecture-based octacore Ryzen desktop CPUs. The final clock speeds and TDPs for the 3 CPUs released in Q1 of 2017 demonstrated significant performance-per-watt benefits over the previous K15h (Piledriver) architecture.[90][91] The octacore Ryzen desktop CPUs demonstrated performance-per-watt comparable to Intel's Broadwell octacore CPUs.[92][93]

In March 2017, AMD also demonstrated an engineering sample of a server CPU based on the Zen architecture. The CPU (codenamed "Naples") was configured as a dual-socket server platform with each CPU having 32 cores/64 threads.[3][9]

Desktop processors
Main article: Ryzen
Ryzen 5 1600 CPU on a motherboard
Threadripper 1950X in socket

First Generation of Ryzen processors (Ryzen 1000 series):

Model Release date
and price		 Fab Chiplets Cores
(threads)		 Core config[lower-roman 1] Clock rate (GHz) Cache Socket PCIe lanes[lower-roman 2] Memory support[lower-roman 3] TDP
Base PBO
1–2
(≥3)		 XFR[94]
1–2		 L1 L2 L3
Entry-level
Ryzen 3 1200[95] July 27, 2017
US $109		 GloFo
14LP		 1 × CCD 4 (4) 2 × 2 3.1 3.4
(3.1)		 3.45 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 2 × 4 MiB
per CCX		 AM4 24 (16+4+4) DDR4-2667
dual-channel		 65 W
Ryzen 3 Pro 1200 [96] July 27, 2017
OEM		 3.1 3.4
(?)		 ?
Ryzen 3 Pro 1300 [97] July 27, 2017
OEM		 3.5 3.7
(?)		 ?
Ryzen 3 1300X[98] July 27, 2017
US $129		 3.5 3.7
(3.5)		 3.9
Mainstream
Ryzen 5 1400 [99] April 11, 2017
US $169		 GloFo
14LP		 1 × CCD 4 (8) 2 × 2 3.2 3.4
(3.4)		 3.45 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 2 × 4 MiB
per CCX		 AM4 24 (16+4+4) DDR4-2667
dual-channel		 65 W
Ryzen 5 Pro 1500 [100] April 11, 2017
OEM		 3.5 3.7
(?)		 ? 2 × 8 MiB
per CCX
Ryzen 5 1500X[101] April 11, 2017
US $189		 3.5 3.7
(3.6)		 3.9
Ryzen 5 1600 [102] April 11, 2017
US $219		 6 (12) 2 × 3 3.2 3.6
(3.4)		 3.7
Ryzen 5 Pro 1600 [103] April 11, 2017
OEM		 3.2 3.6
(?)		 ?
Ryzen 5 1600X [104] April 11, 2017
US $249		 3.6 4.0
(3.7)		 4.1 95 W
Performance
Ryzen 7 1700 [105] March 2, 2017
US $329		 GloFo
14LP		 1 × CCD 8 (16) 2 × 4 3.0 3.7
(3.2)		 3.75 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 2 × 8 MiB
per CCX		 AM4 24 (16+4+4) DDR4-2667
dual-channel		 65 W
Ryzen 7 Pro 1700 [106] March 2, 2017
OEM		 3.4 3.8
(?)		 ?
Ryzen 7 1700X [107] March 2, 2017
US $399		 3.4 3.8
(3.5)		 3.9 95 W
Ryzen 7 1800X [108] March 2, 2017
US $499		 3.6 4.0
(3.7)		 4.1
High-end desktop (HEDT)
Ryzen Threadripper 1900X [109] August 31, 2017
US $549		 GloFo
14LP		 2 × CCD[lower-roman 4] 8 (16) 2 × 4 3.8 4.0
(3.9)		 4.2 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 2 × 8 MiB
per CCX		 TR4 64 (60+4) DDR4-2667
quad-channel		 180 W
Ryzen Threadripper 1920X [110] August 10, 2017
US $799		 4 × CCD 12 (24) 4 × 3 3.5 4.0 4.2 4 × 8 MiB
per CCX
Ryzen Threadripper 1950X [111] August 10, 2017
US $999		 16 (32) 4 × 4 3.4 4.0
(3.7)		 4.2
  1. Active Core Complexes (CCX) × Active cores per CCX.
  2. PCIe lane count includes 4 lanes used for connectivity to the chipset.
  3. Official Support per AMD. CPU's are unlocked for different memory speeds.
  4. Processor package actually contains 4 CCD to provide structural support to the integrated heat spreader (IHS).

Desktop APUs

Ryzen APUs are identified by either the G or GE suffix in their name.

Die shot of an AMD 2200G APU
Model Release Date
& Price		 Fab CPU GPU Socket PCIe lanes Memory
support		 TDP
Cores
(threads)		 Clock rate (GHz) Cache Model Config[lower-roman 1] Clock Processing
power
(GFLOPS)[lower-roman 2]
Base Boost L1 L2 L3
Athlon 200GE[112] September 6, 2018
US $55		 GloFo
14LP		 2 (4) 3.2 N/A 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 4 MiB Vega 3 192:12:4
3 CU		 1000 MHz 384 AM4 16 (8+4+4) DDR4-2667
dual-channel		 35 W
Athlon Pro 200GE[113] September 6, 2018
OEM
Athlon 220GE[114] December 21, 2018
US $65		 3.4
Athlon 240GE[115] December 21, 2018
US $75		 3.5
Athlon 3000G[116] November 19, 2019
US $49		 1100 MHz 424.4
Athlon 300GE[117] July 7, 2019
OEM		 3.4
Athlon Silver 3050GE[118] July 21, 2020
OEM
Ryzen 3 2200GE[119] April 19, 2018
OEM		 4 (4) 3.2 3.6 Vega 8 512:32:16
8 CU		 1126 DDR4-2933
dual-channel
Ryzen 3 Pro 2200GE[120] May 10, 2018
OEM
Ryzen 3 2200G February 12, 2018
US $99		 3.5 3.7 45–65 W
Ryzen 3 Pro 2200G[121] May 10, 2018
OEM
Ryzen 5 2400GE[122] April 19, 2018
OEM		 4 (8) 3.2 3.8 RX Vega 11 704:44:16 1250 MHz 1760 35 W
Ryzen 5 Pro 2400GE[123] May 10, 2018
OEM
Ryzen 5 2400G[124] February 12, 2018[125][126]
US $169		 3.6 3.9 45–65 W
Ryzen 5 Pro 2400G[127] May 10, 2018
OEM
  1. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  2. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Mobile APUs
Model Release
date		 Process CPU GPU Socket PCIe lanes Memory support TDP Part number
Cores
(threads)		 Clock rate (GHz) Cache[lower-roman 1] Model Config[lower-roman 2] Clock Processing
power
(GFLOPS)[lower-roman 3]
Base Boost L1 L2 L3
Athlon Pro 200U [129] 2019 GloFo
14LP		 2 (4) 2.3 3.2 64 KB inst.
32 KB data
per core		 512 KB
per core		 4 MB Vega 3 192:12:4
3 CU		 1000 MHz 384 FP5 12 (8+4) DDR4-2400
dual-channel		 12–25W YM200UC4T2OFB
Athlon 300U [130] January 6, 2019 2.4 3.3 YM300UC4T2OFG
Ryzen 3 2200U [131] January 8, 2018 2.5 3.4 1100 MHz 422.4 YM2200C4T2OFB
Ryzen 3 3200U [132] January 6, 2019 2.6 3.5 1200 MHz 460.8 YM3200C4T2OFG
Ryzen 3 2300U [133] January 8, 2018 4 (4) 2.0 3.4 Vega 6 384:24:8
6 CU		 1100 MHz 844.8 YM2300C4T4MFB
Ryzen 3 Pro 2300U [134] May 15, 2018 YM230BC4T4MFB
Ryzen 5 2500U [135] October 26, 2017 4 (8) 3.6 Vega 8 512:32:16
8 CU		 1126.4 YM2500C4T4MFB
Ryzen 5 Pro 2500U [136] May 15, 2018 YM250BC4T4MFB
Ryzen 5 2600H [137] September 10, 2018 3.2 DDR4-3200
dual-channel		 35–54W YM2600C3T4MFB
Ryzen 7 2700U [138] October 26, 2017 2.2 3.8 Vega 10 640:40:16
10 CU		 1300 MHz 1664 DDR4-2400
dual-channel		 12–25W YM2700C4T4MFB
Ryzen 7 Pro 2700U [139] May 15, 2018 YM270BC4T4MFB
Ryzen 7 2800H [140] September 10, 2018 3.3 Vega 11 704:44:16
11 CU		 1830.4 DDR4-3200
dual-channel		 35–54W YM2800C3T4MFB
  1. AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.[128]
  2. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  3. Single precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Embedded processors

In February 2018, AMD announced the V1000 series of embedded Zen+Vega APUs with four SKUs.[141]

Model Release
date		 Process CPU GPU Memory
support		 Ethernet TDP
(W)		 Junction
temperature (°C)
Cores
(threads)		 Clock rate (GHz) Cache[lower-roman 1] Model Config[lower-roman 2] Clock Processing
power
(GFLOPS)[lower-roman 3]
Base Boost L1 L2 L3
V1500B[142] December 2018 GloFo
14LP		 4 (8) 2.2 N/A 64 KB inst.
32 KB data
per core		 512 KB
per core		 4 MB N/A DDR4-2400
dual-channel		 2× 10GbE 12–25 0–105
V1780B[142] 3.35 3.6 DDR4-3200
dual-channel		 35–54
V1202B[142] February 2018 2 (4) 2.3 3.2 RX Vega 3 192:12:16
3 CU		 1000 MHz 384 DDR4-2400
dual-channel		 12–25
V1404I[142] December 2018 4 (8) 2.0 3.6 RX Vega 8 512:32:16
8 CU		 1100 MHz 1126.4 −40 – 105
V1605B[142] February 2018 0–105
V1756B[142] 3.25 1300 MHz 1331.2 DDR4-3200
dual-channel		 35–54
V1807B[142] 3.35 3.8 RX Vega 11 704:44:16
11 CU		 1830.4
  1. AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.
  2. Unified Shaders : Texture Mapping Units : Render Output Units and Compute Units (CU)
  3. Single-precision performance is calculated from the base (or boost) core clock speed based on a FMA operation.

Server processors
Main article: Epyc
Epyc

AMD announced in March 2017 that it would release a server platform based on Zen, codenamed Naples, in the second quarter of the year. The platform include 1- and 2-socket systems. The CPUs in multi-processor configurations communicate via AMD's Infinity Fabric.[143] Each chip supports eight channels of memory and 128 PCIe 3.0 lanes, of which 64 lanes are used for CPU-to-CPU communication through Infinity Fabric when installed in a dual-processor configuration.[144] AMD officially revealed Naples under the brand name Epyc in May 2017.[145]

On June 20, 2017, AMD officially released the Epyc 7000 series CPUs at a launch event in Austin, Texas.[146]

Model Release date
and price		 Fab Chiplets Cores
(threads)		 Core Config[lower-roman 1] Clock rate (GHz) Cache Socket &
configuration		 PCIe
Lanes		 Memory
support		 TDP
Base Boost L1 L2 L3
All-core Max
EPYC 7351P[147] [148][149] June 2017[150]
US $750		 14 nm 4 × CCD 16 (32) 8 × 2 2.42.9 64 KiB inst.
32 KiB data
per core		 512 KiB
per core		 8 × 8 MiB
per CCX		 SP3
1P		 128 DDR4-2666
8 channels		 155/170 W
EPYC 7401P[147] [148][149] June 2017[150]
US $1075		 24 (48) 8 × 3 2.02.83.0
EPYC 7551P[147][148][149] June 2017[150]
US $2100		 32 (64) 8 × 4 2.55 180 W
EPYC 7251[147][148][149] June 2017[150]
US $475		 8 (16) 8 × 1 2.12.9 8 × 4 MiB
per CCX		 SP3
2P		 DDR4-2400
8 channels		 120 W
EPYC 7261[151] Mid 2018
US $700+		 2.5 8 × 8 MiB
per CCX		 DDR4-2666
8 channels		 155/170 W
EPYC 7281[147][148][149] June 2017[150]
US $650		 16 (32) 8 × 2 2.12.7 8 × 4 MiB
per CCX
EPYC 7301[147][148][149] June 2017[150]
US $800+		 2.2 8 × 8 MiB
per CCX
EPYC 7351[147][148][149] June 2017[150]
US $1100+		 2.42.9 2.9
EPYC 7371[152] Late 2018
US $1550+		 3.1 3.6 3.8 180 W
EPYC 7401[147][148][149] June 2017[150]
US $1850		 24 (48) 8 × 3 2.02.83.0 155/170 W
EPYC 7451[147][148][149] June 2017[150]
US $2400+		 2.32.93.2 180 W
EPYC 7501[147][148][149] June 2017[150]
US $3400		 32 (64) 8 × 4 2.02.63.0 155/170 W
EPYC 7551[147][148][149] June 2017[150]
US $3400+		 2.55 180 W
EPYC 7571 Late 2018
N/A		 2.2 ? 200 W?
EPYC 7601[147][148][149] June 2017[150]
US $4200		 2.73.2 180 W
  1. Active Core Complexes (CCX) × Active cores per CCX.

Embedded Server processors

In February 2018, AMD also announced the EPYC 3000 series of embedded Zen CPUs.[153]

Model Release
date		 Fab Cores
(threads)		 CPU die count Enabled CCX Count Core Config Clock rate (GHz) Cache[lower-roman 1] Socket PCIe

lanes

 Memory
support		 Ethernet TDP Junction temperature (°C) Part Number
Base Boost L1 L2 L3
All-core Max
EPYC 3101 February 2018 14nm 4 (4) 1 2 4+0 2.12.92.9 64 KB inst.
32 KB data
per core		 512 KB
per core		 8 MB SP4r2 32 DDR4-2666
dual-channel		 4 × 10GbE 35 W 0-95 PE3101BIR4KAF
EPYC 3151 4 (8) 2+2 2.72.92.9 16 MB

(8 MB per CCX)

 45 W PE3151BJR48AF
EPYC 3201 8 (8) 4+4 1.53.13.1 DDR4-2133
dual-channel		 30 W PE3201BHR88AF
EPYC 3251 8 (16) 2.53.13.1 DDR4-2666
dual-channel		 55 W 0-105 PE3251BGR88AF
EPYC 3255 Un­known 25-55 W -40-105 PE3255BGR88AF
EPYC 3301 February 2018 12 (12) 2 4 3+3+3+3 2.02.153.0 32 MB

(8 MB per CCX)

 64 DDR4-2666
quad-channel		 8 × 10GbE 65 W 0-95
EPYC 3351 12 (24) 1.92.753.0 SP4 60-80 W 0-105 PE3351BNQCAAF
EPYC 3401 16 (16) 4+4+4+4 1.852.253.0 SP4r2 85 W
EPYC 3451 16 (32) 2.152.453.0 SP4 80-100 W PE3451BMQGAAF
  1. AMD defines 1 kilobyte (KB) as 1024 bytes, and 1 megabyte (MB) as 1024 kilobytes.[154]


See also

References
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