V850

The basis of V810 and V850 is a typical general-purpose registers-based load/store architecture.[51]^:4 They have 32 of 32-bit general-purpose registers, and R0 is fixed as Zero Register which contains always zero. In V850, R30 is implicitly used by SLD/SST; 16-bit short format load/store instructions as element pointer (ep),which addressing mode comprises base address register ep and immediate operand offsets. In V850E or later microarchitectures, R3 is also implicitly used by PREPARE/DISPOSE; call stack frame creation and unwinding instructions, as stack pointer. Compilers' calling convention also uses R3 as the stack pointer.

Original V850 has simple 5-stage 1-clock pitch pipeline architecture.[48]^:114–126 These are the significant feature of RISC; reduced instruction set computers. But object code size is about the half of that of MIPS R3000.[51]^:5 because V810 and V850 adopted 16-bit and 32-bit 2-way form length instruction format respectively,[48]^:38–40[51]^:17[52]^:29–30 and the most of frequently used instructions are mapped into 16-bit half-word. In other words, 16-bit external bus width is relatively enough to provide instructions continuously without pipeline stalling, which enables low power consumption on the application board, and is suitable for mobile equipments. This concept is similar to Renesas (formerly, Hitachi) SH, ARM Thumb, and MIPS16 instruction set architectures.[53]^:4

In addition, implementing instruction set is cautiously selected. For example, function call with Jump and (Register) Link instruction,[48]^:61[51]^:20[52]^:64 which save next PC on a register (fixed to R31 in V810), is also one of RISC technique to reduce the number of instructions. Return from the function can be done by jmp [Rn] (jmp [R31] in V810) instruction.[48]^:61[51]^:23[52]^:65 Typical CISC processors use call & return instructions and push the next PC on their stack memory area.

But V810 and V850 have some microarchitecture differences. V810 adopts microprogram operation method for some instructions; floating-point arithmetic and bit string operations, while V850 is a hundred percent hardwired control method. As the result, for example, the first V850 does not have floating-point arithmetic and bit manipulation instruction sets; including the "find first one/zero" (search 1/0; SCH1x/SCH0x), except for "set/clr/negate a bit" (SET1/CLR1/NOT1). Those extended instruction sets are revived in V850E2x extensions.

Though V800 Series adopts RISC instruction set architecture, their assembly language is hand-coding friendly. They adopt straight forward load/store architecture.[51]^:4 In addition, the "interlock" mechanism both for the data hazards and for the branch hazards are implemented,[51]^:33–35 in other words, assembly language programmer does not need to consider any delay slots. 32 general-purpose registers provide flexibility for assembly language users. Mixture of hand-assembled codes and C language compiled codes is available by using compiler options, such as "-mno-app-regs" in Gnu Compiler Collection.[54]

It is a little bit pity that IN instruction of V810 is removed from the first V850, which enables unsigned-load from memory-mapped I/O.[51]^:22[52]^:63

Detailed discussion is available in some old journals.[55][56]

Main purpose of the modification of V810 to V850 is saturation arithmetic because of customers' requestcustomers' request.

V850 Series repeated many microarchitecture extension, but all the extensions have backward compatibility.[57] In other words, all the old binary software assets, including written in a quarter century ago, work on every new core. In addition, each microarchitecture has circuit implementation variants and fabrication process technology variants across a quarter century.

In 1996, V853 was announced as the first 32-bit RISC microcontroller with integrated flash memory.[58] But its maximum number of "erase and write" cycles were 16 counts.[59]^:37

In 1998, NEC strategically started to expand V850 product line both in standard and ASSP business and in ASIC and SoC business.[60]

The first generation of V850 does not have unsigned load instructions, which was removed from V810 (as IN.H and IN.B), then it was added again as LD.HU and LD.BU in the second generation; V850E (V850E1) Series. In addition, V850E has some other user-friendly CISCy extensions such as "call table," "switch," and "prepare/dispose".[61]^:217

In 2001, NEC launched V850ES core, which is ultra-low-power series, but is ISA compatible with V850E.[62]

Around 2001, Java Acceleration IP core for V850 seemed to be provided to some customers as SoC,[63] but detailed information is in some patents only.[64][65]

In 2005, NEC Electronics introduced V850E2 core as V850E2/ME3 product line with super-scalar architecture.[66]

In 2009, NEC Electronics introduced V850E2M as dual-core with 2.56MIPS/MHz and 1.5 mW/MIPS.[67]

In 2011, Renesas disclosed SIMD extension for V850 as V850E2H.[57][68] As for SIMD extension, some academic studies were done.[69] But architectural documentation for this latest product line is disclosed to automotive customers only. It can not be found on Renesas' web site.[70] Its name seems to be changed to V850E3 or G3H. The only way to know about its instruction set is to do "reverse engineering" from the GNU Compiler Collection.

The original V810 and V850 CPU architecture is designed for ultra-low power applications.

Detailed description of the V810 is described in some journals.[71][72]

According to Renesas's documentation, power consumption of V850ES/Jx3-L implementation is about 70% of ARM Cortex-M3.[5]^:14,15

The V810 operates at from 2.2 V to 5.5 V  with 5 V 0.8 μm (CZ4) fabrication process,[73] which power dissipation with Dhrystone MIPS are 500 mW with 15MIPS and 40 mW with 6 MIPS at 5 V and 2.2 V, respectively. It is one of the most low power 32-bit microcontroller product in the early 1990s. This specification can be achieved both by well considered instruction set architecture and by precisely tuned 5-stage 1-clock pitch pipeline microarchitecture, both of them are the benefit of the simplified RISC feature.

This ultra-low power DNA is succeeded by V850/Sxn product line, those are still alive in mass production over 20+ years. Most of them are produced with 3.3 V with 0.35μm (UC1) fabrication process, which CPU core is precisely tuned to operate from 1.8 V to 3.6 V, working at 32.768 kHz (sub-osc.) to 16.78 MHz (main-osc.) with internal oscillator amplifier plus external resonator (crystal or ceramic).[10] Its power dissipation is 2.7 mW/MIPS for 3.3 V 0.35 μm (UC1) fabrication process, and 3.6 mW/MIPS for 5 V 0.35 μm (CZ6) fabrication process. "Software STOP" stand-by mode for mask ROM version of V850/SA1, which internal watch timer operates at 3.3 V with 32.768 kHz sub-oscillator (I_DD6), consumes typically 8 μA electrical current only. And, Subclock normal operation mode at 3.3 V with 32.768 kHz consumes 40 μA typically, 140 μA at the maximum. (I_DD5)[74]^:440,IDD5[13] Its 1.8 V typical CPU operation current at 32.768 kHz might be 22 μA (40 μA ÷ 3.3 V × 1.8 V), which power dissipation should become 40 μW. It corresponds to 1.0 mW/MIPS (40 μW ÷ 0.032768 MHz ÷ 1.15 DMIPS/MHz ÷ 1000).
The V850/Sxn product line is also tuned for low noise both with EMI and with EMS. Especially, V850/SB1 and SB2 are specially tuned for low EMI noise with 5 V internal voltage regulator, which enables high sensitivity of receiving RF for car radio.[75]^:41–44

In 2011, NEC launched 3rd generation microarchitecture V850ES ultra-low-power series, which insists 1.43 mW/MIPS at operating voltage range from 2.2 V to 2.7 V,[62] but this first implementation of V850ES microarchitecture seems to be incomplete compared with later generations of the same architecture. Its "Sub-IDLE" stand-by mode for mask ROM version of V850ES/SA2 and V850ES/SA3, those internal RTC operate at 2.5 V with 32.768 kHz sub-oscillator (I_DD6), consume typically 5 μA electrical current only. But, Subclock normal operation mode at 2.5 V with 32.768 kHz consume 40 μA typically, 100 μA at the maximum.[76]^:509 Its 2.2 V typical CPU operation current at 32.768 kHz might be 31 μA (40 μA ÷ 2.5 V × 2.2 V), which power dissipation should be 68 μW. It is about 1.7 times of V850/SA1. It corresponds to 1.6 mW/MIPS (68 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000).

The V850ES/JG3-L product line has ultra-low power variants, named μPD70F3792, 793 and μPD70F3841, 842. They can operate from 2.0 V to 3.6 V with 18 μA typical electrical current at 32.768 kHz,[77]^{:1002, 1041} which should be 22 μW at 2.0 V (18 μA × 2.0 V ÷ 3.3 V × 2.0 V). It corresponds to 0.52 mW/MIPS (22 μW ÷ 0.032768 MHz ÷ 1.3 DMIPS/MHz ÷ 1000). In addition, their sub-clock idle mode, with watch timer, power consumption should be typically 3.4 μW at 1.8 V (3.5 μA ÷ 3.3 V × 1.8 V × 1.8 V).[77]^{:1002, 1041}

The power consumption of NA85E2 (V850E2) core is much larger compared with NU85E (V850E1) core in the same CB-12L (UX4L)[73][78] fabrication process. The reason is that V850E2x core has 128-bit width instruction prefetch bus and plural of Instruction Prefetch Queues,[79]^:16 while average instruction length of V800 Series is almost 16-bit.[51]^:17 It means 16 instructions are possibly fetched from the memory at once, then the memory and the prefetcher circuits sleep rest 3 to 7 cycles for dual-pipeline superscalar architecture. This gap enlarges electrical current amplitude differences. In addition, the peak electric current exceeds allowance for the voltage stabilizers of mobile gadgets. As for V850E2M CPU core, it is publicly introduced as 1.5 mW/MIPS, 3 times of former generations, although it should have advantages of new fabrication process technologies.[67] Some mobile equipment avoids using dual-instruction execution (dual-pipeline superscalar), in other words, adopting the single-instruction (single-pipeline) execution setting to reduce electrical current amplitude differences.

V810 mounted on PC‑FXGA (in Japanese)[80] Gaming Accelerator board.
Marked as "©NEC 1991."

Nintendo Virtual Boy employed customized V810. 14x20mm² packge (on left) is marked "©NEC '91, '93."

Because the V850 Family[48]^:16 is developed as a branch of V800 Series,[3]^:97,PDF103 the basic CPU architecture is inherited from V810.[81] Instruction set architecture of the first V850 is drastically modified from that of V810, but the difference is within a patch level from GNU Compiler Collection point of view.[82] The main purpose of this change is to implement saturation arithmetic by customers' request.

Detailed design methodology of V810 is described in a journal.[83] V850 utilizes this design assets. But datapath logic was changed from dynamic logic to static logic, to enable 32.768 kHz real-time clock frequency operation mode.

The register-transfer level "CPU architecture design" of the V810 is developed with the Functional Description Language (FDL)[84][85][86] on the Falcon Simulator software, those are NEC's in-house CAD tools. This methodology is the same as that of NEC V60.[87] In the late 1980s, the Verilog HDL has not acquired by Cadence Design Systems yet.[88] The FDL had been used until the middle of the 2000s, and was also used for the development of NEC's super-computer; named Earth Simulator.[89]

The difference from V60 is that the circuit diagram was written with schematic editor, not of Calma, but of Mentor Graphics called NETED,[90] a part of the Design Architect product[91][92] on Apollo Computer's workstation, which is the most major schematic editor at that moment.[93] It enabled to generate netlists, such as EDIF and SPICE, for LVS program like cadence's Dracula products, and NEC's in-house and Zycad netlist for logic simulation. Later on, this circuit diagram of NETED became able to generate gate-level Verilog HDL netlist for V850.

Most of the register-transfer level FDL netlist was translated to the gate-level schematic by hand, because the logic synthesis has not yet to be practical use at that moment. The FDL was divided into datapath and random logic precisely. For the datapath part, the gate-level circuit diagram enabled manually repeated artwork. On the other hand, for the random logic part, logic synthesis was tried to use for generating gate-level schematic, but it was about 10% of the total circuit.

In addition, formal verification has also not to be practical use yet, which means full regression test by dynamic logic simulation is required for gate-level netlist to compare with RTL one. For gate-level logic simulation, NEC's in-house CAD tool named V-SIM is usually used.[94] But sometimes hardware emulator, such as Zycad LE simulation accelerator,[95] is used for this purpose. (Refer to:.[96]^:13 In this material, the performance of Zycad LE is compared with NEC's HAL, but initial design decade differs.[97])

Each opcode (operation code) table is from User's Manual: Architecture (refer to external links.).

• 1st map opcodes

All the opcode (operation code) of the hardwired control operation is closed within the first 16-bit half-word, more precisely, the first 7 bits from MSB. A 64-word depth ROM structure with branch condition code table is enough for decoding hardware. If a 16-bit literal operand is required, it is located in the second half-word. Microprogram control operations; bit strings and floating-point arithmetic instructions, are also located in the second 16-bit half-word. As the result, all the instructions become 16-bit and 32-bit 2 way form length. Unsigned load form memory mapped I/O is implemented as In instruction. Arithmetic and logical instructions are not fully but relatively orthogonal.

V810 does not have saturation arithmetic instructions, but 1 additional instruction in format II, such as SAT which checks flags (Overflow, Sign, Zero, and Half-word) and rewrites specified register, might be enough both for signed and unsigned, and for word and half-word, arithmetic operations.

Bit [12:10] [15:13, 9]	000	001	010	011	100	101	110	111	Format
000 X	MOV	ADD	SUB	CMP	SHL	SHR	JMP	SAR	I(R,r)
001 X	MUL	DIV	MULU	DIVU	OR	AND	XOR	NOT
010 X	MOV	ADD	SETF	CMP	SHL	SHR		SAR	II(imm5,r)
011 X	TRAP	RETI	HALT		LDSR	STSR		Bit str.
100 0 100 1	Bcond								III(disp9)
	BV	BZ/BE	BN(BS)	BLT	BNV	BNZ/BNE	BP(BNS)	BGE
	BC/BL	BNH	BR	BLE	BNC/BNL	BH	NOP	BGT
101 X	MOVEA	ADDI	JR	JAL	ORI	ANDI	XORI	MOVHI	IV/V
110 X	LD.B	LD.H		LD.W	ST.B	ST.H		ST.W	VI(disp16[R],r)
111 X	IN.B	IN.H	CAXI	IN.W	OUT.B	OUT.H	Float	OUT.W	VI/VII

"NOP" is an alias of "Non-BR".

• 1st map opcodes

Bit [7:5] [10:8]	000	001	010	011	100	101	110	111	Format
000	MOV	NOT	DIVH	JMP	SATSUBR	SATSUB	SATADD	MULH	I(R,r)
001	OR	XOR	AND	TST	SUBR	SUB	ADD	CMP
010	MOV	SATADD	ADD	CMP	SHR	SAR	SHL	MULH	II(imm5,r)
011	SLD.B				SST.B				IV(disp7[ep],r)
100	SLD.H				SST.H				IV(disp8[ep],r)
101	Bit[0] SLD.W / SST.W				Bit[3:0] Bcond				IV/III
110	ADDI	MOVEA	MOVHI	SATSUBI	ORI	XORI	ANDI	MULHI	VI(disp16[R],r)
111	LD.B	2nd Map	ST.B	2nd Map	JARL		Bit[15:14] SET1/NOT1 /CLR1/TST1	2nd Map Extension	V/VII/VIII

"NOP" is an alias of "MOV R0,R0".

• 2nd map opcodes

Bit [23:21]	000	001	010	011	100	101	110	111	Format
[16]	1st Map  Bit[10:5]=111001
0	LD.H								VII
1	ST.H								VII
[16]	1st Map  Bit[10:5]=111011
0	LD.W								VII
1	ST.W								VII
[26:24]	1st Map  Bit[10:5]=111111
000	SETF	LDSR	STSR	undef	SHR	SAR	SHL	undef	IX(R,r)
001	TRAP	HALT	RETI	1st Map Bit[15:13] EI/DI undef	Illegal instruction				X
01X	Illegal instruction								—
1XX	Illegal instruction								—

• 1st map opcodes

Bit [7:5] [10:8]	000	001	010	011	100	101	110	111	Format
000	—†	NOT	SWITCH	JMP	ZXB	SXB	ZXH	SXH	I(R,r0)
	MOV		DBTRAP	Bit[4] SLD.BU /SLD.HU	SATSUBR	SATSUB	SATADD	MULH	I(R0,r31) / IV
			undef						I(R0,r) / IV
			DIVH						I(R,r) / IV
001	OR	XOR	AND	TST	SUBR	SUB	ADD	CMP	I(R,r)
010	CALLT		ADD	CMP	SHR	SAR	SHL	undef	II(imm5,r0)
	MOV	SATADD						MULH	II(imm5,r)
011	SLD.B				SST.B				IV(disp7[ep],r)
100	SLD.H				SST.H				IV(disp8[ep],r)
101	Bit[0] SLD.W / SST.W				Bit[3:0] Bcond				IV/III(disp9)
110	ADDI	Bit[15:11] MOV(r=0)	Bit[15:11] DISPOSE(r=0)		ORI	XORI	ANDI	Bit[15:11] undef	VI(imm16,R,r) /VI(imm32,R) /XIII
		MOVEA	MOVHI	STASUBI				MULHI
111	LD.B	2nd Map	ST.B	2nd Map			Bit[15:14] SET1/NOT1 /CLR1/TST1	2nd Map	VII(disp16[R],r) /VIII(imm3,disp16[R])

†:"NOP" is an alias of "MOV R0,R0".

• 2nd map opcodes

Bit [23:21] [16, 26:24]	000	001	010	011	100	101	110	111	Format
	1st Map  Bit[10:5]=111001
0 XXX	LD.H								VII(disp16[R],r)
1 XXX	ST.H
	1st Map  Bit[10:5]=111011
0 XXX	LD.W								VII(disp16[R],r)
1 XXX	ST.W
	1st Map  Bit[10:5]=11110X
0 XXX	1st Map  Bit[15:11]  JR(r=0) / JARL (r≠0)								V(disp22)
1 XXX	1st Map  Bit[15:11]  PREPARE(r=0) / LD.BU								XIII/VII(disp16[R],r)
	1st Map  Bit[10:5]=111111
0 000	SETF	LDSR	STSR	undef	SHR	SAR	SHL	Bit[18:17] SET1/NOT1 CLR1/TST1	IX(R,r) IX(R,[r])
0 001	TRAP	HALT	Bit[18:17] RETI/CTRET /DBRET /undef	1st Map Bit[15:11] EI/DI undef	undef				X
0 010	SASF	Bit[17] MUL(R,r,w) /MULU(R,r,w)	Bit[17] MUL(imm9,r,w) /MULU(imm9,r,w)		Bit[17] DIVH(R,r,w) /DIVHU(R,r,W)		Bit[17] DIV(R,r,w) /DIVU(R,r,w)		IX(R,r) /XI(R,r,w) /XII(imm9,r,w)
0 011	CMOV(imm5,r,w)	CMOV(R,r,w)	Bit[18:17] BSW/BSH HSW/undef	undef	Illegal instruction				XI(c,R,r,w) /XII(c,imm5,r,w)
0 10X	Illegal instruction
1 XXX	LD.HU								VII(disp16[R],r)

In 1998, NEC started to provide V850 Family as an ASIC core to expand its ASIC business.[113] In addition, both the V850E1 CPU core named Nx85E[114][115] and the V850E2 CPU core named Nx85E2,[116] respectively, are also used for expanding its standard products business with ASIC design methodology.
Various SoC utilize this core. For example, in 2003, Dotcast, Inc. used NU85E core for a set top box receiver of the digital datacasting based on dNTSC (data in NTSC video[117]) method. This core is fabricated with CB-10 0.25μm process technology which adopts 5 layered metal.[118]^:9–10

The NA85E2C core, which is developed in 1.5 V 150 nm CB-12L (UX4L)[73][78] fabrication process, has many errata (4 pages appendix in preliminary architecture manual,[119]^:230–233 plus 7 pages another restrictions document,[120] as long as disclosed on the web). But it seems not to be a matter for uses, because this is long-running product.

NEC also expanded the core for 130 nm CB-130 (UX5) fabrication process[73] cell-base IC, but it is unclear.[121][122]

Synopsys DesignWare® IP core for V850E was once announced,[123] but support obsoleted.[124]

FPGA prototyping systems for V850E1, V850E2, and V850E2M core based SoC were intensively developed to expand SoC business. They comprised a V850 CPU core LSI (TEG^†) board and "FPGA add-on"s. Most of SoC products were for mobile equipments; because the power dissipation of original V800-Series RISC architecture was much lower compared with CISC.[1][5][101] It is the same logic as the ARM (which stands for Acorn RISC Machine) architecture is widely used for mobile gadgets.

†TEG: Test Element Group

• Renesas (NEC): COREBEST (2001)[135][136][137]

• Renesas (NEC): Microssp (2006)[111]

• Renesas (NEC): Hybrid Emulator (2007)[138]

• Renesas (NEC): PFESiP® EP1 Evaluation Board (2008)[139]

• Renesas (NEC): PFESiP® EP1 Evaluation Board Lite (2008)[140]

• Renesas (NEC): PFESiP® EP3 Evaluation Board (2010): V850E2M CPU core, max. 266 MHz operation[141]

• Xylon: logicBRICS[142][143]

• Red Hat, Inc.: The Newlib for C runtime library (libc.a) and mathematical lirary (libm.a)[174]

C runtime startup routine (crt0.S) for the latest v850e3v5 microarchitecture is available.[175][176][177]

• Micro Digital Inc.: GoFast® for NEC V85x Fast Software Floating Point Library[178]
• The GNU Compiler Collection: Software floating point[179]
• The GNU Compiler Collection: Decimal floating point (libdecnumber.a)[180]

Operating systems of V850 are mostly real-time operation towards.

Some of operating systems require the Memory Protection Unit (MPU) to divide tasks (or threads) strictly for reliability and safety reasons. In such cases, v850e2v3 (Gen. 3) microarchitecture or above are required.

ITRON is an open standard specification of real-time OS (RTOS), which is major in Japan. Its specification is defined under leadership of Ken Sakamura as a part of TRON project. Initial letter I stands for "Industrial." Because ITRON specification defines interface and skeleton only, each vendor has its own taste of implementation.

• Renesas:
  • RI850MP Real-time OS for V850E2M Dual Core[181]
  • RI850V4 V2 Real-time OS for RH850 Family[182]
  • RI850V4 V1 Real-time OS for V850 Family[183]

• Toppers Project: Open source TOPPERS/JSP

→ In 2003, on Rel. 1.3, V850 dedicated part bug was fixed.[184]

→ Kernel update history[185]

• A.I. Corporation: Toppers-Pro/xxx[186]
• T-Engine Project: Open source T-Kernel by TRON Forum[187]
• eSOL: eT-Kernel; Extended T-Kernel — RTOS for embedded systems[188][189]
  • eT-Kernel/Compact, eT-Kernel/Embedded, eT-Kernel/POSIX
  • eT-Kernel Multi-Core Edition
• eCos: Open source real-time operating system

AUTOSAR is an open systems architecture of operating system for automotive industry. Its purpose is to establish the standardization of ECU; Electronic Control Unit for automotive engines. AUTOSAR is an upward compatible specification of OSEK/VDX, which is also a consortium name of Germany established in 1993.

In Japan, this research was started in 2006 as a joint project by JAIST and DENSO. Renesas Electronics joined this project in 2009.[190] Because the current RH850 and V850 processors are principally targeted at the automotive industry, it is one of a strategical product of Renesas Electronics. However, its documentation is only available in Japanese as its main customer is Toyota Motor Corporation.

• Renesas: RV850 (documents are in Japanese only)[191]
• ETAS GmbH: RTA-OS RH850/GHS,[192] RTA-OSEK V850E/GHS[193]
• Mentor Graphics (formerly Accelerated Technology, Inc.): Nucleus OSEK[194]
• HighTec EDV-Systeme GmbH: EB tresos Safety OS[195]
• Toppers Project: Open source TOPPERS/AUTOSAR[196]
• eSOL: eMCOS AUTOSAR profile[197]

• SYSGO AG:
  • PikeOS; Embedded Virtualization Hypervisor[198][199][200][201]

• eSOL:
  • eMCOS; Scalable RTOS, Distributed Microkernel Architecture, non-hypervisor type OS[202]

• MiSPO:
  • NORTi Professional; Real-time OS + TCP/IP stack + Simulator[203]

• SEGGER
  • embOS V850 NEC, embOS V850 Green Hills, embOS V850 IAR[204][205][206]

• Wind River Systems:
  • VxWorks®: Ported in the early 1990s.[207]
    The Tornado® IDE is stated that MP licenses has been sold via NEC in 2000, currently Renesas.[208]

• Mentor Graphics (formerly ATI, currently A Siemens Business):
  • Nucleus PLUS[158][209]

• uCLinux[162][210]
• Linux kernel

On October 9th 2008, Linux kernel support for V850 was removed in revision 2.6.27,[163] preventing the possibility of porting Android.[168]

Various middleware application softwares are provided from various vendors.

• Renesas: SD Memory Card Control[211]

Most of the compilers, both for the V850 Family; and for the RH850 Family, are exactly the same product, and extended ISA targets are controlled by "command line options."[212][213]

Compilers for the V850 Fmily and the RH850 Family include:

• The GNU Compiler Collection (the name is still v850 for RH850)[214] developed both:
  • by "Red Hat, Inc." (formerly "Cygnus Solutions") as a part of the GNUPro Developers Kit[215]
  • by "KMC (Kyoto Micro Computer)" as a part of the exeGCC[158][216][217]
  • by "CyberTHOR Studios, Ltd.": Free pre-built binaries can be downloaded by registration.[218]

• Renesas:
  • C Compiler Package for V850 Family[219]
    • CA850 C compiler for V850E1 and V850ES (v850e1 and/or v850es, a.k.a. Gen. 1)[220]
    • CX C compiler for V850E2M and V850E2S (v850e2v3, a.k.a. Gen. 3)
  • Software Package for V850 [SP850] for V850E2 (v850e2(v2), a.k.a. Gen. 2)[221]
  • CC-RH C compiler package for G3, G3K(H), G3M(H)[222]

• GHS (Green Hills Software): The Green Hills Optimizing Compilers[223][224]

• Wind River Systems: Diab Compiler[225][226]

• IAR Systems: Embedded Workbench[227]

• Altium Limited: Tasking®; RENESAS RH850 SOFTWARE DEVELOPMENT TOOLS[228]

• HighTec EDV Systeme GmbH: HighTec Development Platform[229][230]

• GAIO Technology: XASS-V Series cross development tools[158][231][232]

• Metrowerks: CodeWarrior (obsoleted)[158]

Usually, dis-assemblers are provided as a part of C compiler or assembler packages.

e.g.)

• The GNU Binutils: objdump (v850-elf-objdump or v850-elf32-objdump)[233]

• Radare2: Radare2 is a set of command-line programming tools for reverse engineering.[234] Open-source code is available from GitHub repository.[235][236]

• IDA Pro: IDA Pro is a freeware disassembler for hobby use. A plugin for V850 is available. Download site is gray for securities.[237]

GUI based program debuggers are mainly provided for debugging of compiled source codes. Usually, it is used with instruction set simulators or in-circuit emulators.

• Renesas:
  • ID850: For the combination of CA850 compiler and SM850 instruction set simulator.
  • ID850NW: For the combination of N-Wire based in-circuit emulators.
  • ID850QB: For the combination of probing-pod based emulator IEQUBE2
• NDK (Naito Densei Kogyo Co. Ltd, Group): Operation started in 1950 as subsidiary of NEC.
  • NW-V850-32
• GHS (Green Hills Software): Multi: General-purpose debugger.
• Red Hat, Inc.: Insight (GDB-Tk): GUI front-end tightly combined with GNU Debugger.
• Mentor Graphics (formerly Accelerated Technology, Inc.): code|lab Developer Suite[238]
• By N-Wire based in-circuit emulator vendors:
  • KMC (Kyoto Microcomputer) and Midias Lab.: PARTNER[239]
  • Sohwa & Sophia Technologies:WATCHPOINT[240]
  • DTS INSIGHT (formerly YDC, Yokogawa Digital Computer): microVIEW-PLUS
  • Computex: CSIDE

Instruction set simulator, in other words, Virtual Platform is provided to perform debugging without equipment's hardware before testing on a real machine.

• Renesas: SM850[241]
• Open Virtual Platform: Instruction set simulator[242]
• Synopsys: VDK for Renesas RH850 MCU[243]

Automated code reviewer, in other words, source code analyzer qualify the level of completeness of written software source code. This method is classified as dynamic code analysis and static code analysis.

• Renesas: TW850

TW850 Performance Analysis Tuning Tool is a general utility to improve effectiveness of software.[244]

• Renesas: AZ850

AZ850 System Performance Analyzer is a utility for RX850 real-time operating system to evaluate effectiveness of application programs.[245]

• Gaio Technology: Coverage Master winAMS[246]

Coverage Master winAMS is a source code coverage measurement tool.

• GHS (Green Hills Software): DoubleCheck ISA (Integrated Static Analysis) tool[247]

• Rogue Wave Software, Inc: Klocwork[248]

IDE, Integrated Development Environment, is a framework to provide software development functions.

• Renesas: CS+ (formerly CubeSuite+)[249]
• GHS (Green Hills Software): Multi
• Eclipse Plugins
  • GNU Compiler Collection (GCC) and GNU Debugger (GDB)
  • Wind River Workbench (formerly Tornado®)

Most of in-circuit emulators, such as Rnesas IE850 (formerly IECUBE2) ,[250] can be used both for V850 Family and for RH850 Family, but may require firmware updating. The latest "trace function" of the JTAG (N-Wire[251] ) based in-circuit emulator is replaced from the N-Trace (single-ended signaling)[252] to the Aurora Trace (differential signaling).[253]

Full probing pod type in-circuit emulator is sometimes called as full ICE or legacy ICE.

• Renesas IE850 (formerly IECUBE2)[250]
• Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.)
  • Asmis brand for custom LSIs.[254]

• Lauterbach: ROM Monitor for V850[255]^:5
• KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-ET II (obsoleted)[256]

N-Wire and N-Trace[257][252][258][259] is a JTAG-based debugging interface specification, which circuit implementation is called TAP Controller (Test Access Port controller),[260] primarily compiled by Philips N.V. (currently NXP Semiconductors) about a quarter century ago. But it is perhaps not disclosed publicly in its earlier stage. As the result, each semiconductor and in-circuit emulator vendor implemented similar interfaces independently. Nowadays, it is standardized by IEEE 1149.1 Working Group.[261]

• Renesas
  • E1 Emulator:[262] USB 2.0 based affordable compact housing equipment.
  • PCMCIA N-Wire Card IE-V850E1-CD-NW[263]

• Naito Densei Machida Mfg. Co., Ltd. (Operation started as NEC's subsidiary.): Asmis brand.[264]
• Midas Lab.: RTE-2000H[265] with PARTNER[127][239] debugger
• Lauterbach: Trace32[255][266][267]
• iSystem: BlueBox iC5000 and iC5700[268][269]
• IAR Systems
• DTS INSIGHT (formerly YDC; Yokogawa Digital Computer): adviceLUNA II[270][271]

• Computex: PALMiCE3 V850[272]
• Sohwa & Sophia Technologies: Universal Probe Blue[273] with WATCHPOINT debugger[240]
• KMC (Kyoto Microcomputer Co., Ltd.): PARTNER-Jet (obsoleted)[274]

Nexus or IEEE-ISTO 5001-2003 is a standard debugging interface for embedded systems.
Aurora is a high speed signal transfer specification. Its data link layer communications protocol is a point-to-point serial links, and physical layer is a high speed differential signaling.

• Lauterbach: Trace32: PowerTrace for NEXUS[275]
• iSystem: BlueBox iC5000 and iC5700 (Nexus), iC6000 (Aurora)[276][277]

Because V850 Family is developed as a single chip microcontroller, every product integrates non-volatile memory. In its first stage, it was one-time programmable or UV EPROM type, but V853, V850/xxn Series and later, it becomes flash memory type.

A gang writer, or a gang programmer, is an old terminology for programmable ROM writers, or programmers. Its name origin comes from that it steals the binary code from one device, and write it to plural ones simultaneously. This read device is sometimes called as a master device. For mass production use, a dedicated attachment board with "a set of sockets," i.e. "a gang," is needed. As usual, instead of a programmed master device, an object code file can be copied from a PC via download cable, or from a USB stick. Most of gang writers accept ASCII format files such as Intel HEX and Motorola SREC, or binary format files such as ELF.

This method is suitable for mass production.

• TESSERA Technology Inc.: Stick GANG Writer[278]

Flash ROM programming service providers exit in most of countries.

• Minato Holdings, Inc.

Minato Holdings, Inc. (in Japanese)[279] is a Japanese company started as an automated test equipment vendor for memory LSIs. Nowadays, it provides flash ROM programming service for various devices, including V850 and RH850, with its own made gang writers and full automatic device handler machines.

Most of JTAG-based in-circuit emulators have an on board flash ROM programming function via debug port.
May be or may not be IEEE standard 1532-2002; a standard for in-system configuration of programmable components.[280]

If the target board has a RS-232C connector and a transceiver (driver/receiver) IC, such as ICL32xx,[281] for the UARTx peripheral function of V850 device, flash ROM programming with directly connected PC might be available (depends on devices[282]^:16–24 ). The Renesas Flash Programmer software V2[283] or V3[284] is required.

On board programming is also available via UARTx or CSIx+HS peripheral on V850 devices by using dedicated programmer hardware (depends on devices[282]^:16–24).

• Renesas: PG-FP6[285]

To program V851[286]^:11,14–20 and V852,[287]^:11,14–20 an ancient PROM programmer with dedicated adapter is required.

• Renesas PG-1500 (obsoleted)

Renesas PG-1500[288] is a programmable ROM writer compatible with 27C1001A[289] devices, UV EPROM or OTP; one-time PROM. This writer reads silicon signature[290][291] from each device before programming by asserting 12.5 V to A9 (address #9) terminal. It must NOT be used for modern flash ROM burning.

Some gray zone hacking tools exit for V850 on car dashboards.

• VVDI PROG.:
  • OBDexpress[292]

• Renesas: TK-850: The naming is anachronic nostalgia of TK-80; 8080-based training kit.